DataSheet.es    


PDF DP5380 Data sheet ( Hoja de datos )

Número de pieza DP5380
Descripción Asynchronous SCSI Interface (ASI)
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de DP5380 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! DP5380 Hoja de datos, Descripción, Manual

May 1989
DP5380 Asynchronous SCSI Interface (ASI)
General Description
The DP5380 ASI is a CMOS device designed to provide a
low cost high performance Small Computer Systems Inter-
face It complies with the ANS X3 131-1986 SCSI standard
as defined by the ANSI X3T9 2 committee It can act as
both INITIATOR and TARGET making it suitable for any
application The ASI supports selection reselection arbitra-
tion and all other bus phases High-current open-drain driv-
ers on chip reduce application chip count by interfacing di-
rect to the SCSI bus An on-chip oscillator provides all tim-
ing delays
The DP5380 is pin and program compatible with the NMOS
NCR5380 device NCR5380 or AM5380 applications can
use it with no changes to hardware or software The
DP5380 is available in a 40-pin DIP or a 44-pin PCC
The ASI is intended to be used in a microprocessor based
application and achieves maximum performance with a
DMA controller The device is controlled by reading and
writing several internal registers A standard non-multi-
plexed address and data bus easily fits any mP environment
Data transfers can be performed by programmed-I O pseu-
do-DMA or via a DMA controller The ASI easily interfaces
to a DMA controller using normal or Block Mode The ASI
can be used in either a polled or interrupt-driven environ-
ment
Features
SCSI Interface
Y Supports TARGET and INITIATOR roles
Y Parity generation with optional checking
Y Arbitration support
Y Direct control monitoring of all SCSI signals
Y High current outputs drive SCSI bus directly
Y Faster and improved timing
Y Very low SCSI bus loading
mP Interface
Y Memory or I O-mapped control transfers
Y Programmed-I O or DMA data transfers
Y Normal or Block-mode DMA
Y Fast DMA handshake timing
Connection Diagram
Table of Contents
1 0 FUNCTIONAL DESCRIPTION
2 0 PIN DESCRIPTION
3 0 REGISTER DESCRIPTION
4 0 DEVICE OPERATION
5 0 INTERRUPTS
6 0 RESET CONDITIONS
7 0 APPLICATION GUIDE
8 0 ABSOLUTE MAXIMUM RATINGS
9 0 DC ELECTRICAL CHARACTERISTICS
10 0 AC ELECTRICAL CHARACTERISTICS
A1 FLOWCHARTS
A2 REGISTER CHART
TL F 9756 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
PAL is a registered trademark of and used under license from Monolithic Memories Inc
C1995 National Semiconductor Corporation TL F 9756
RRD-B30M115 Printed in U S A

1 page




DP5380 pdf
2 0 Pin Descriptions (Continued)
Symbol DIP
PCC
Type
Function
REQ
20 22 I O Request driven by the TARGET and received by the INITIATOR as part of the REQ
ACK handshake
I O 17 19 I O Input Output driven by the TARGET to control the direction of transfers on the
SCSI bus This signal also distinguishes between selection and reselection
C D 18 20 I O Command Data driven by the TARGET to indicate whether command or data bytes
are being transferred
MSG
19 21 I O Message driven by the TARGET during message phase to identify message bytes
on the bus
VCC
GND
31 35
11 12 13
VCC GND a5V DC is required Because of very large switching currents good
decoupling and power distribution is mandatory
2 1 Connection Diagrams
Order Number DP5380N
See NS Package Number N40A
TL F 9756 – 4
Order Number DP5380V
See NS Package Number V44A
TL F 9756 – 5
5

5 Page





DP5380 arduino
4 0 Device Operation (Continued)
The interface to the DMA controller uses the DRQ DACK
EOP lines in non-block mode Each byte is requested (DRQ)
and ack’d (DACK) Representative timing for a DMA read is
shown in Figure 4 8 1
if(BSR Busy error OR NOT
(BSR End of DMA))
error routine
else
*DMA End*
MR2 4 04h
*reset DMA bit*
ICR 4 0
TL F 9756 – 7
FIGURE 4 8 1 Non-Block DMA Timing
4 8 1 NON-BLOCK DMA
DMA operation involves programming the ASI with the set-
up parameters initiating the DMA cycles and checking for
correct operation when the completion interrupt is received
The DMA controller should be programmed with the data
byte count and the memory start address Methods of halt-
ing a DMA operation are covered in Section 4 11
Setting up the ASI requires enabling or disabling the follow-
ing Data bus driving DMA mode enable BSY monitoring
EOP interrupt parity checking parity interrupt TARGET
Mode bus phase
Once set up DMA should be initiated by writing to address 5
6 or 7 as appropriate The DMA controller should assert
EOP during the transfer of the last byte although this may
be done by the mP if the DMA transfers (n b 1) bytes and
the mP transfers the last byte See the application guide for
more details (Section 7 0)
Upon completion the mP should check the following as re-
quired End of DMA Parity Error Phase Match Busy Error
The end of DMA occurs as a response to EOP SCSI trans-
fers may still be underway so REQ and ACK must still be
checked to establish when the final byte is finished
The code below shows programming of the ASI in each of
the four DMA cases One of these cases is shown in a flow
diagram in Appendix A
Initiator Send
*DATA OUT PHASE*
Program DMA Controller
TCR 4 00h
*phase*
ICR 4 01h
*Assert DBUS*
MR2 4 0Eh
SDS 4 00
*Start DMA Send*
while (NOT interrupt)
idle
while (CSD REQ)
idle
*wait for last
SCSI byte
transfer so phase
is checked*
Initiator Receive
*DATA IN PHASE*
Program DMA Controller
TCR 4 01h
*phase*
MR2 4 3Eh
SDI 4 0
*Start DMA Init
Rx*
while (NOT interrupt)
idle
*no need to wait for last SCSI handshake
done since DMA done implies it is
checked*
if(BSR parity error OR BSR busy error
or NOT (BSR End of DMA)
do error routines
else
*End of DMA*
while (CSD REQ)
idle *wait for REQ inactive
to deassert ACK*
MR2 4 04h
Target Receive
*DATA OUT PHASE*
Program DMA Controller
TCR 4 0
*phase*
ICR 4 08h
MR2 4 7Ah
*check parity*
SDT 4 0
*Start DMA Targ Rx*
while (not interrupt)
idle
*when End of DMA occurs the last byte
has been read and checked*
if(BSR parity error OR NOT(BSR End of DMA)
error routine
else
*End of DMA*
while (BSR ACK)
idle
*Not True End of DMA so wait until SCSI
bus inactive before changing phase*
MR2 4 40h
change phase as required
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet DP5380.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
DP5380Asynchronous SCSI Interface (ASI)National Semiconductor
National Semiconductor
DP5380DP5380 Asynchronous SCSI Interface (ASI) (Rev. A)Texas Instruments
Texas Instruments

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar