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PDF R65C51 Data sheet ( Hoja de datos )

Número de pieza R65C51
Descripción ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER
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R65C51
ASYNCHRONOUS COMMUNICATIONS
DESCRIPTION
PRELiMlNARY
FEATURES
The Rockwell CMOS R65C51 Asynchronous Communications
Interface Adapter (ACIA) provides an easily implemented, pro-
gram controlled interface between 8-bit microprocessor-based
systems and serial communication data sets and modems.
The ACIA has an internal baud rate generator. This feature elim-
inates the need for multiple component support circuits, a crystal
being the only other part required. The Transmitter baud rate
can be selected under program control to be either 1 of 15 dif-
ferent rates from 50 to 19,200 baud, or at l/16 times an external
clock rate. The Receiver baud rate may be selected under pro-
gram control to be either the Transmitter rate, or at l/16 times
the external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'12, or
2 stop bits.
The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardware implementa-
tion. Three separate registers permit the MPU to easily select
the R65C51’s operating modes and’ data checking parameters
and determine operational status.
The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.
Low power CMOS N-well silicon gate technology
Direct replacement for NMOS R6551 ACIA
Full duplex operation with buffered receiver and transmitter
Data set/modem control functions
Internal baud rate generator with 15 programmable bau
rates (50 to 19,200)
. Program-selectable internally or’externally controlled receive
rate
. Programmable word lengths, number of stop bits, and pant
bit generation and detection
Programmable interrupt control
Program reset
Program-selectable serial echo mode
Two chip selects
1 or 2 MI-Q operation
5.0 Vdc t 5% supply requirements
28-pin plastic or ceramic DIP
Full TTL compatibility
Compatible with. R6500, R6500/’ and R65COO micro-
processors
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
--
The Status Register indicates the states of the IRQ, DSR, and
DCD lines. Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions,
The Transmitter and Receiver Data Registers are used for tem-
porary data storage by the ACIA Transmit and Receiver circuits.
ORDERING INFORMATION
Part No.: R65C51
-
Temperature Range (TL to TH):
Blank = 0% to +70°C
E= -40% to +85%
Frequency Range:
1 = 1 MHz
2 = 2 MHz
Package:
C = Ceramic
P = Plastic
Document No. 29651 N60
2-296
Figure 1. R65C51 AClA Pin Configuration
Product Description Order No. 2157
Rev. 3, October 1984

1 page




R65C51 pdf
R65C51
Asynchronous Communications Interface Adapter (ACIA
COMMAND REGISTER
The Command Register controls specific modes and functions.
76543210
PMC
TIC
PME REM 1
- IRD DTR
PNCl PNCO
TIC1 TIC0
Bits 7-6
76
‘i;j- 0
01
10
11
Parity Mode Control (PMC)
Odd parity transmitted/received
Even parity transmitted/received
Mark parity bit transmitted
Parity check disabled
Space parity bit transmitted
Parity check disabled
Bit 5
0
1
Parity Mode Enabled (PME)
Parity mode disabled
No parity bit generated
Parity check disabled
.
Parity mode enabled
Bit 4
0
1
Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode bits 2 and 3
Must be zero for receiver echo mode, m
be low.
will
Bits 3-2
32
00
01
10
11
Transmitter Interrupt Control (TIC)
RTS = High, transmitter disabled
RTS = Low, transmit interrupt enabled
RTS = Low, transmit interrupt disabled
I?% = Low, transmit interrupt disabled
transmit break on TxD
Bit 1
0
1
Receiver Interrupt Request Disabled (IRD)
IRQ enabled (receiver)
IRQ disabled (receiver)
Bit 0
0
1
Data Terminal Ready (DTR)
Data terminal not ready (m high)’
Data terminal ready (fi low)
NOTE
‘The transmitter is disabled immediately. The receiver is
disabled but will first complete receiving a byte in process
of being received.
Data Terminal Ready (Bit 0)
This bit enables all selected interrupts and controls the state o*
the Data Terminal Ready (m) line. A 0 indicates the micro-
computer system is not ready by setting the DTR line high. b
1 indicates the microcomputer system is ready by setting the
DTR line low. fi line low. m also enables and disables
the transmitter and receiver.
Receiver Interrupt Control (Bit 1)
This bit disables the Receiver from generating an interrupt whee
set to a 1. The Receiver interrupt is enabled when this bit is SE
to a 0 and Bit 0 is set to a 1.
Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (m)
the Transmitter interrupt.
line an’
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 disables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
0. In the Receiver Echo Mode, the Transmitter returns eact
transmission received by the Receiver delayed by one-half bi-
time.
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disable:
parity bit generation by the Transmitter and parity bit checking
by the Receiver. A 1 bit enables generation and checking c
parity bits.
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Trans
mitter, (even, odd, mark or space) and the type of parity chec
done by the Receiver (even. odd, or no check).
Reset Initialization
76543210
I~olololo~o~o~o~o~
--11-1. -t ]ojo~O~O~o,
Hardware reset (m)
Program reset
2-300

5 Page





R65C51 arduino
a
R65CSl
Asynchronous Communications Interface Adapter (ACM
Overrun in Echo Mode
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as a normal overrun in Receive Mode. For the re-
transmitted data, when overrun occurs, the TxD line goes to the
“MARK” condition until the first Start Bit after the Receiver Dar
Register is read by the processor. Figure 12 shows the timir
relationship for this mode.
\
IRQ t
/i
\ nJ) I
1
b
1 RI
A
PROCESSOR
INTERRuFT
FOR RECEIVER
OATA REGISTER
REAO RECEIVER
PROCESSOR
REAOS
STATUS
REGISTER
OVERRUNOCCURS
TxO GOES To
“MARK”
CONDITION
PROCESSOR FINALLY
READS RECEIVER
DATA REGISTER.
LAST VALIO
CHARACTER
(=nb
t
TxO DATA
RESUMES
PROCESSOR
INTERRUPT
FOR CHAR *JI
IN RECEIVER
DATA REGISTER
Figure 12. Overrun in Echo Mode
Framing Error
Framing Error is caused by the absence of Stop Bit(s) on
received data. A Framing Error is indicated by the setting of bit
4 in the Status Register at the same time the Receiver Data
Register Full bit is set, also in the Status Register. In response
to m, generated by RDRF, the Status Register can also be
checked for the Framing Error. Subsequent data words a
tested for Framing Error separately, so the status bit will alwa
reflect the last data word received. See Figure 13 for Framl
Error timing relationship.
RX0
(EXPECTED)
RR0
(ACTUAL)
NOTES:
1. FRAMING ERROR DOES NOT
INHISIT RECEIVER OPERATION.
2. IF NEXT DATA WORD IS OK.
FRAMING ERROR IS CLEARED.
/
clMISSING
STOP
SIT
Figure 13. Framing Error
I
PROCESSOR
INTERRUPT,
FRAMING
ERROR
BIT SET

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