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PDF ST22N256 Data sheet ( Hoja de datos )
| Número de pieza | ST22N256 | |
| Descripción | Smartcard 32-Bit RISC MCU | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST22N256
Smartcard 32-Bit RISC MCU with 256 Kbytes EEPROM
Javacard™ HW Execution & Cryptographic Library
DATA BRIEF
PRODUCT FEATURES
I 32-BIT RISC CPU WITH 24-BIT LINEAR
MEMORY ADDRESSING
I 368 KBYTES USER ROM
I 16 KBYTES USER RAM
I 256K KBYTES USER EEPROM
32-BIT RISC CPU
I DUAL INSTRUCTION SET, JAVACARD™
AND NATIVE
I 4-STAGE PIPELINE
I 16 GENERAL PURPOSE 32-BIT REGISTERS,
AND SPECIAL REGISTERS
I 4 MASKABLE INTERRUPT LEVELS
I SUPERVISOR AND USER MODES
SECURITY
I CPU SECURITY INSTRUCTIONS
– DES and 3DES instructions
– Fast Multiply and Accumulate instructions for
Public Key and Elliptic Curve Cryptography
– CRC instruction
I RANDOM NUMBER GENERATOR
I EEPROM FLASH PROGRAMMING MODE
I CLOCK AND POWER MANAGEMENT
I VOLTAGE AND CLOCK FREQUENCY
SENSORS
I ADVANCED MEMORY PROTECTION
– Memory Protection Unit for application
firewalling and peripheral access control
– Domain switching securely controlled by
protected Context Stack
– Native/Java, Code/Data memory attributes
with 128-byte granularity
I FOUR WORKING STACKS
– Java stack with both 16 and 32-bit accesses
– User and Supervisor mode stacks
– Security Context stack
Figure 1. Delivery Form
Micromodule
Wafer
CRYPTOGRAPHIC LIBRARY
I ASYMMETRICAL ALGORITHMS
– Software Crypto libraries in separate ROM
area for efficient algorithm coding using a set
of advanced functions. RSA, signature/
verification.
– RSA key calculation including Prime number
generation SHA-1
I SYMMETRICAL ALGORITHMS
– DES, Triple DES, AES
CRYPTOGRAPHY PERFORMANCE
The following table provides the cryptographic
performances of the ST22N256 based on ST
Crypto Library.
Table 1. Preliminary Cryptographic
Performances
Algorithm
RSA
1024 bits
RSA
2048 bits
DES
SHA-1
AES-128
Function
Signature with CRT
Signature without CRT(2)
Verification (e=0x10001)
Signature with CRT
Signature without CRT
Verification (e=0x10001)
Triple
Single
512-bit Block
Encryption including subkey
computation
Time(1)
79.0 ms
242.0 ms
3.6 ms
485.0 ms
1.7 s
11.0 ms
18 µs
8 µs
194 µs
85 µs
1. Internal clock at 33 MHz
2. CRT: Chinese Reminder Theorem
June 2004
For further information contact your local ST sales office.
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ST22N256
SOFTWARE DEVELOPMENT ENVIRONMENT
Modularity, flexibility and methodology are the key
words for the SmartJ™ Development Tools Plat-
form. Using the same interface, the developers are
able to create, compile and debug a project.
The SmartJ™ Integrated Development environ-
ment (IDE) includes:
– A code Generation chain: C/C++ compiler,
assembler and linker. The assembler supports
both native and JavaCard™ instruction sets.
– An instruction set simulator, a cycle accurate
simulator, a C/C++ source level debugger and
hardware emulation tools.
OEM DEVELOPMENT LICENSE TYPES
The ST22N256 is a product based on the
SmartJ™ Platform. Developers have two types of
licenses for access to the technology:
I STLDA
The SmartJ™ Technology License and Distri-
bution Agreement for Standard OEM Develop-
ers (Embedded Operating System and Applica-
tion Software developers) and Card Embed-
ders.
They must use the SmartJ™ Hardware Soft-
ware Interface (HSI) meta-layer communication
interface to access the product hardware re-
sources. The validation of the Embedded Soft-
ware will be done using the Simulators of the
Code Validation Tools chain.
I SPTLA (not yet available)
The SmartJ™ Platform Technology License
Agreement for OEM Platform Developers. The
SPTLA is for developers who need to develop a
customised architecture using the platform
blocks assembled with a proprietary custom
hardware plug-in logic block and associated
firmware. The complete Code Validation Tools
chain including the VHDL Emulator, must be
used for both the hardware, software develop-
ment integration and validation. The complete
Code Validation Tool chain is accessible to
OEM Platform Developers licensees only.
Figure 3. SmartJ™ Platform Concept
SmartJ Platform
ST22 Core Plus
SmartJ IDE
SmartJ H/W Development
(not yet available)
SmartJ
ISO 15408 Certified
Embedded Library
ROM RAM NVM
Size Definition
STD PERIPHERALS
& SECURITY
ASI, Timers, Security
Mechanisms,...
CUSTOMS PLUGS-IN (1)
SmartJ-Tools Pack-CD
VHDL Library (1)
Note: 1) SmartJ™ Platform Technology License Agreement required
2) SmartJ™ Technology License and Distribution Agreement required
HSI (2)
Memory & Std Peripherals Drivers
CRYPTO (2)
Certified Crypto Library
(DES, 3DES, RSA, SHA, AES...)
484
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| PDF Descargar | [ Datasheet ST22N256.PDF ] | |
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