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PDF IMISM561 Data sheet ( Hoja de datos )
| Número de pieza | IMISM561 | |
| Descripción | Spread Spectrum Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Features
• 54- to 166-MHz operating frequency range
• Wide (9) range of spread selections
• Accepts clock and crystal inputs
• Low power dissipation
• 3.3V = 165 mw. (Fin = 120 MHz)
• Frequency spread disable function
• Center spread modulation
• Low cycle-to-cycle jitter
• Eight-pin SOIC package
Block Diagram
SM561
Spread Spectrum Clock Generator
Applications
• High-resolution VGA controllers
• LCD panels and monitors
• Workstations and servers
Benefits
• Peak electromagnetic interference (EMI) reduction by 8 to
16 dB
• Fast time to market
• Cost reduction
Pin Configuration
250 K
Xin/ 1
CLK
4 pf
Xout 8
VDD 2
VSS 3
8 pF
REFERENCE
DIVIDER
MODULATION
CONTROL
INPUT
DECODER
LOGIC
5
SSCC
67
S1 S0
PD CP
FEEDBACK
DIVIDER
Xin/CLK 1
VDD
2
LF
VSS
3
SSCLK
4
VCO
DIVIDER
AND MUX
4 SSCLK
8 Xout
7 S0
6 S1
5 SSCC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07021 Rev. *C
Revised December 14, 2002
1 page  
SM561
SSCG Theory of Operation
The SM561 is a PLL-type clock generator using a proprietary
Cypress design. By precisely controlling the bandwidth of the
output clock, the SM561 becomes a Low EMI clock generator.
The theory and detailed operation of the SM561 will be
discussed in the following sections.
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e., third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multilayer PCBs, etc. The SM561 uses the approach of
reducing the peak energy in the clock by increasing the clock
bandwidth, and lowering the Q.
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
both peak and cycle to cycle. The SM561 takes a narrow band
digital reference clock in the range of 54–166 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand
what happens to a clock when SSCG is applied, consider a
65-MHz clock with a 50% duty cycle. From a 65-MHz clock we
know the following, as illustrated here.
50 %
50 %
Tc = 15.4 ns
Clock Frequency = fc = 65 MHz
Clock Period = Tc =1/65 MHz = 15.4 ns
If this clock is applied to the Xin/CLK pin of the SM561, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition from F1 to F2, the amount of time and sweep
waveform play a very important role in the amount of EMI
reduction realized from an SSCG clock.
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. Figure 1 also shows the
modulation profile of a 65-MHz SSCG clock. Notice that the
actual sweep waveform is not a simple sine or sawtooth
waveform. Figure 2 is a scan of the same SSCG clock using
a spectrum analyzer. In this scan you can see a 6.48-dB
reduction in the peak RF energy when using the SSCG clock.
Modulation Rate
Spectrum Spread Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmr.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the part. The SM560 and SM561
have a fixed divider count, as listed below.
Document #: 38-07021 Rev. *C
Page 5 of 8
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IMISM561.PDF ] | |
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