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PDF TA1270BF Data sheet ( Hoja de datos )

Número de pieza TA1270BF
Descripción PAL/NTSC VIDEO AND CHROMA SYNC PROCESSING SYSTEM FOR PIP/POP/PAP
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



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TA1270BF
TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA1270BF
PAL / NTSC VIDEO CHROMA AND
SYNC PROCESSING SYSTEM FOR PIP / POP / PAP
TA1270BF is a PAL / NTSC color TV signal processor IC suitable
for PIP / POP / PAP. The IC integrates video, chroma and sync
processor circuits. It comes in a 48pin flat package.
The video block uses a chroma trap, the chroma block a PAL /
NTSC automatic identifier circuit, and the sync processor block a
50 / 60 Hz automatic identifier circuit. The PAL demodulator
circuit contains a baseband signal processor, making the circuit
adjustment free.
The TA1270BF incorporates an I2C bus, enabling control to be set
via the bus line.
FEATURES
Video block
l Chroma trap
l Y delay line
l Sub contrast adjustment (±3 dB)
Weight: 0.83 g (Typ.)
CHROMA block
l UV / CbCr demodulation for NTSC ; UV demodulation for PAL
l Tint control
l PAL demodulation baseband signal processing
l PAL / NTSC automatic identification
l Sub color adjustment (±3 dB)
Sync processor block
l High-performance sync separator circuit
l Adjustment-free horizontal and vertical oscillator circuit using count down method
l 50 / 60 Hz automatic identifier circuit
Switch block
l High-speed switcher circuit
l YUV or RGB input
l Built-in RGB matrix circuit
l YUV or RGB output
1 2002-12-24

1 page




TA1270BF pdf
PIN
No.
PIN NAME
FUNCTION
13 VP output
Vertical pulse output pin
INTERFACE
TA1270BF
INPUT / OUTPUT
SIGNAL
14 HD output
Outputs HD pulse processed by the
AFC. HD output phase or pulse width
can be changed by bus setting.
15 SCP output
Outputs sand castle pulse (SCP).
The output signals are clamp pulse,
horizontal blanking pulse, and
vertical blanking pulse.
The minimum load resistance is
3 k.
16 Dig GND
Logic block GND pin
17 CP / HP input
Input pin for CP / HP pulse used to
operate the SW circuit.
CP is used as clamp pulse ; HP as
blanking pulse.
18 SYNC VCC
19 SW VCC
VCC pins for sync processor block
and SW block.
Connect 9 V (Typ.).
7.9 V
4.3 V
2.5 V
5 2002-12-24

5 Page





TA1270BF arduino
PARAMETER
V-FREQ / AFC-G
B-Y / R-Y
BLACK LEVEL ADJ.
GP-PHS
Y-OFST
OUTPUT MODE
HD-PHS
(0) : PHASE-1
TA1270BF
DESCRIPTION
Controls vertical frequency and horizontal free run.
V FREQUENCY
AFC-Gain
(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)
AUTO1
(50 / 60 Hz MODE)
60 Hz MODE
262.5H forced
312.5H forced
AUTO2
(50 / 60 Hz MODE)
60 Hz mode
262H forced
312H forced
Normal
Normal
Free run
Free run
Normal
Normal
Free run
Free run
V pull-in range
224.5H~353H
224.5H~297H
32.5H~353H
32.5H~297H
Adjusts B-Y / R-Y black level ; 68 mV~+68 mV
Switches gate pulse phase ; (0) : Normal , (1) : 200 ns (Ahead)
Switches Y output offset ; +10 IRE : ON / OFF
(0) : OFF, (1) : ON
Switches SW output mode.
Switches YUV / RGB (matrix coefficient) output.
(00) : Y / U / V, (01) : RGB / PAL, (10) : RGB / NTSC1,
(11) : RGB / NTSC2
POWER-ON
INITIAL VALUE
(000)
AUTO1
(100000)
CENTER
Normal
OFF
(00)
Y/U/V
(1) : PHASE-2 (SCP)
Read function
PARAMETER
PORSET
COLOR SYSTEM
X’tal
V-FREQ
V-STD
H-LOCK
N-DET
Y2-IN, U2 / V2-IN
DESCRIPTION
Power-on reset.
(0) : RESISTER PRESET, (1) NORMAL
Color system. Received system (ID, no ID)
(00) : B / W, (01) : SECAM, (10) : PAL, (11) : NTSC
X’tal mode
(00) : , (01) : 4.43 (N), (10) : M, (11) : 3.58
Vertical frequency ; (0) : 50 Hz, (1) : 60 Hz
Decides vertical standard ;
(0) : STANDARD, (1) : NON-STANDARD
Decides horizontal lock ; (0) : LOCK, (1) : UN-LOCK
Decides noise level ; (0) : Low, (1) : High
Outputs self diagnosis result. ; (0) : NG, (1) : OK
11
2002-12-24

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