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PDF K5D5657DCM-F015 Data sheet ( Hoja de datos )

Número de pieza K5D5657DCM-F015
Descripción MCP / 256Mb NAND and 256Mb Mobile SDRAM
Fabricantes Samsung Electronics 
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No Preview Available ! K5D5657DCM-F015 Hoja de datos, Descripción, Manual

K5D5657DCM-F015
Preliminary
MCP MEMORY
MCP Specification of
256Mb NAND and 256Mb Mobile SDRAM
- 1 - Revision 0.0
June 2003

1 page




K5D5657DCM-F015 pdf
K5D5657DCM-F015
PIN DESCRIPTION
Pin Name
CLK
CKE
/CS
/RAS
/CAS
/WEd
A0 ~ A12
BA0 ~ BA1
LDQM
UDQM
DQ0d ~ DQ15d
Vdd
Vddq
Vss
Vssq
Pin Function(Mobile SDRAM)
System Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Input
Bank Address Input
Lower Input/Output Data Mask
Upper Input/Output Data Mask
Data Input/Output
Power Supply
Data Out Power
Ground
DQ Ground
Preliminary
MCP MEMORY
Pin Name
/CE
/RE
/WP
/WE
ALE
CLE
R/B
IO0 ~ IO7
Vcc
Vccq
Vss
Pin Function(NAND Flash)
Chip Enable
Read Enable
Write Protection
Write Enable
Address Latch Enable
Command Latch Enable
Ready/Busy Output
Data Input/Output
Power Supply
Data Out Power
Ground
Pin Name
NC
DNU
Pin Function
No Connection
Do Not Use
ORDERING INFORMATION
K 5 D 56 57 D C M - F 0 15
Samsung
MCP Memory(2chips)
Device Type
NAND Flash + Mobile SDRAM
NAND Flash Density,
Organization
56 : 256Mbit, x8
Mobile SDRAM Density, Organization
57 : 256Mbit, x16
Mobile SDRAM Speed
15 = 15ns, CL=2
NAND Flash Speed
0 = None
Package
F = FBGA(Leaded)
Version
M= 1st Generation
Operating Voltage
D: 2.6V / 1.8V
Flash Block Architecture
C = Uniform Block
NOTE :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose,
such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
- 5 - Revision 0.0
June 2003

5 Page





K5D5657DCM-F015 arduino
K5D5657DCM-F015
Preliminary
MCP MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
2013
Typ.
-
Max
2048
Unit
Blocks
NOTE :
1. This device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. The 2nd and 3rd blocks are good upon shipping.
AC TEST CONDITION
( Vcc=2.4V~2.9V , TA=-40 to 85°C)
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (VccQ:2.65V +/-10%)
Value
0V to VccQ
5ns
VccQ/2
1 TTL GATE and CL=30pF
CAPACITANCE(TA=25°C, VCC=2.65V , f=1.0MHz)
Item
Symbol
Test Condition
Input/Output Capacitance
Input Capacitance
CI/O
CIN
VIL=0V
VIN=0V
NOTE : Capacitance is periodically sampled and not 100% tested.
Min
-
-
Max
10
10
MODE SELECTION
CLE ALE
CE
WE
RE PRE WP
Mode
HL L
LHL
HXX
Command Input
Read Mode
HXX
Address Input(3clock)
HL L
LHL
HXH
Command Input
Write Mode
HXH
Address Input(3clock)
LLL
H X H Data Input
L L LH
X X Data Output
X X X X X X H During Program(Busy)
X X X X X X H During Erase(Busy)
X X(1) X X X X L Write Protect
X X H X X 0V/VCC(2) 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Program Time
tPROG
-
200 500
Dummy Busy Time for the Lock or Lock-tight Block
tLBSY
-
5 10
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
2
3
Block Erase Time
tBERS
-
2
3
Unit
pF
pF
Unit
µs
µs
cycles
cycles
ms
- 11 -
Revision 0.0
June 2003

11 Page







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