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PDF ICX224AK Data sheet ( Hoja de datos )

Número de pieza ICX224AK
Descripción CCD Image Sensor with Square Pixel for Color Cameras
Fabricantes Sony 
Logotipo Sony Logotipo



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ICX224AK
Diagonal 8mm (Type 1/2) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX224AK is a diagonal 8mm (Type 1/2)
interline CCD solid-state image sensor with a square
pixel array and 2.02M effective pixels. Frame
readout allows all pixels' signals to be output
independently within approximately 1/7.5 second.
Also, the adoption of high frame rate readout mode
supports 30 frames per second which is four times
the speed in frame readout mode. This chip features
an electronic shutter with variable charge-storage
time. Adoption of a design specially suited for frame
readout ensures a saturation signal level equivalent
to when using field readout. Ye, Cy, Mg, G
complementary color mosaic filters are used as the
color filters, and at the same time high sensitivity and
low dark current are achieved through the adoption
of Super HAD CCD technology.
This chip is suitable for applications such as electronic
still cameras, PC input cameras, etc.
20 pin DIP (Plastic)
Pin 1
Features
V
Supports frame readout
High horizontal and vertical resolution
Supports high frame rate readout mode: 30 frames/s
Square pixel
Horizontal drive frequency: 18MHz
4
Pin 11
H
48
No voltage adjustments (reset gate and substrate bias are not adjusted.)
Ye, Cy, Mg, G complementary color mosaic filters on chip
Optical black position
High sensitivity, low smear
(Top View)
Continuous variable-speed shutter
Low dark current, excellent anti-blooming characteristics
20-pin high-precision plastic package (top/bottom dual surface reference possible)
2
10
Device Structure
Interline CCD image sensor
Image size:
Diagonal 8mm (Type 1/2)
Total number of pixels: 1688 (H) × 1248 (V) approx. 2.11M pixels
Number of effective pixels: 1636 (H) × 1236 (V) approx. 2.02M pixels
Number of active pixels: 1620 (H) × 1220 (V) approx. 1.98M pixels
Chip size:
7.6mm (H) × 6.2mm (V)
Unit cell size:
3.9µm (H) × 3.9µm (V)
Optical black:
Horizontal (H) direction: Front 4 pixels, rear 48 pixels
Vertical (V) direction: Front 10 pixels, rear 2 pixels
Number of dummy bits: Horizontal 28
Vertical 1 (even fields only)
Substrate material:
Silicon
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98926C99

1 page




ICX224AK pdf
ICX224AK
Clock Equivalent Circuit Constant
Item Symbol
Capacitance between vertical transfer
clock and GND
CφV1A, CφV3A
CφV1B, CφV3B
CφV2, CφV4
CφV1A2, CφV3A4
CφV1B2, CφV3B4
CφV23A, CφV41A
Capacitance between vertical transfer
clocks
CφV23B, CφV41B
CφV1A3A
CφV1B3B
CφV1A3B, CφV1B3A
CφV24
CφV1A1B, CφV3A3B
Capacitance between horizontal transfer CφH1
clock and GND
CφH2
Capacitance between horizontal transfer
clocks
CφHH
Capacitance between reset gate clock
and GND
CφRG
Capacitance between substrate clock
and GND
CφSUB
R1A, R3A
Vertical transfer clock series resistor
R1B, R3B
R2, R4
Vertical transfer clock ground resistor RGND
Horizontal transfer clock series resistor RφH
Min.
Typ.
390
1800
1800
220
470
120
330
120
120
270
330
180
120
120
30
8
820
75
100
120
30
5
Max.
Unit Remarks
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Vφ2
Vφ1A
CφV24
CφV1A2
R1A
R2
CφV1A3A
CφV23B
CφV23A
Vφ3A
R3A
CφV1B2
CφV1A
CφV1A1B
CφV1B3A
CφV1B
CφV41A
CφV2
CφV3A
CφV3A3B
CφV1A3B
CφV3B
R1B
Vφ1B
CφV4
CφV41B
RGND
CφV1B3B
CφV3A4
CφV3B4
R3B
Vφ3B
R4
RφH
Hφ1
RφH
Hφ1
CφHH
CφH1
RφH
RφH
Hφ2
Hφ2
CφH2
Vφ4
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
–5–

5 Page





ICX224AK arduino
ICX224AK
Readout modes
The diagram below shows the output methods for the following two readout modes.
1st field
Frame readout mode
2nd field
High frame rate readout mode
VOUT
9G
8 Ye
7G
6 Ye
5G
4 Ye
3G
2 Ye
1G
Mg 9 G
Cy 8 Ye
Mg 7 G
Cy 6 Ye
Mg 5 G
Cy 4 Ye
Mg 3 G
Cy 2 Ye
Mg
VOUT
1G
Mg 9 G
Cy 8 Ye
Mg 7 G
Cy 6 Ye
Mg 5 G
Cy 4 Ye
Mg 3 G
Cy 2 Ye
Mg 1 G
VOUT
Mg
Cy
Mg
Cy
M
g
Cy
Mg
Cy
Mg
Note) Blacked out portions in the diagram indicate pixels which are not read out.
Output starts from the line 5 in high frame rate readout mode.
1. Frame readout mode
In this mode, all pixel signals are divided into two fields and output.
All pixel signals are read out independently, making this mode suitable for high resolution image capturing.
2. High frame rate readout mode
All effective area signals are output in 1/4 the period for frame readout mode by reading out two lines for
every eight lines. The number of output lines is 325 lines.
This readout mode emphasizes processing speed over vertical resolution.
– 11 –

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