PDF QT82C881 Datasheet ( Hoja de datos )

Número de pieza QT82C881
Descripción FireLink 1394 OHCI Link Controller
Fabricantes Opti 
Logotipo Opti Logotipo

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QT82C881 Hoja de datos, Descripción, Manual
FireLink 1394 OHCI
Link Controller
Preliminary Data Book
Revision 1.0
December 13, 1999

1 page

QT82C881 pdf
FireLink 1394 OHCI
® 82C881
1.0 Features
Supports asynchronous and isochronous transfers at
100, 200 and 400 Mbps
The OPTi 82C881 1394 OHCI Link Controller is a PCI-
based host controller with the following features.
Implements a fully Bus Manager Capable node
including an Isochronous Resource Manager
Compliant with PCI Local Bus Specification 2.1
Compliant with P1394a Draft 2.0 Standard for a High-
performance Serial Bus
Interfaces to 33MHz, 32-bit PCI bus
PnP (Plug and Play) compatible per PCI Local Bus
Specification rev. 2.1
Interfaces to PHYs that conform to the Link-PHY
interface described in Chapter 5 of the P1394a Draft
2.0 specification
Interfaces to 1394-1995 compliant PHYs
Offers selective disabling of 1394a features
(controllable by software) for interfacing to a partially
P1394a compliant PHY
Implements IEEE1212-based control and status
registers that can be mapped to both I/O and memory
Incorporates independent DMA controllers for
isochronous and asynchronous operations
Supports four isochronous transmit and isochronous
receive contexts
Supports burst transactions on the PCI bus interface
Offers direct access to the physical address space of
the host
Assigns priority for DMA per 1394 OHCI specification
Supports four transmit and three receive configurable
Offers both packet per-buffer and buffer-fill modes of
operation for the isochronous receive context
Supports posting of physical write request packets
Complies with the PCI Power Management
specification rev. 1.1, supporting ACPI states D0 and
D3hot and PME# generation
Incorporates CLKRUN# support
Implements comprehensive Debug Registers
Implements physical upper bound register.
2.0 Overview
This document describes the OPTi FireLink 1394 OHCI
Link Controller (82C881). It details:
Signal Definitions
Strap Selectable Options
Register Descriptions.
Incorporates two wire industry-standard Serial
EEPROM interface
Functions as a 1394 cycle master
FireLink 1394 System Block Diagram
Revision: 1.0
Page 1

5 Page

QT82C881 arduino
FireLink 1394 OHCI
3.4 Signal Descriptions
3.4.1 PCI Bus Interface Signals
Signal Name
Refer to
28, 41,
53, 65
52 O
43 I/O
Signal Description
Address and Data Lines 31 through 0: This bus carries the address and/or
data during a PCI bus cycle. A PCI bus cycle has two phases - an address phase
which is followed by one or more data phases. During the initial clock of the bus
cycle, the AD bus contains a 32-bit physical byte address. AD[7:0] is the least
significant byte (LSB) and AD[31:24] is the most significant byte (MSB). After the
first clock of the cycle, the AD bus contains data.
When the 82C881 is the target, AD[31:0] are inputs during the address phase.
For the data phase(s) that follow, the 82C881 may supply data on AD[31:0] in the
case of a read or accept data in the case of a write.
When the 82C881 is the master, it drives a valid address on AD[31:2] during the
address phase, and drives write or accepts read data on AD[31:0] during the data
phase. As a master, the 82C881 always drives AD[1:0] low.
Bus Command and Byte Enables 3 through 0: These signals provide the
command type information during the address phase and carry the byte enable
information during the data phase. C/BE0# corresponds to byte 0, C/BE1# to byte
1, C/BE2# to byte 2, and C/BE3# to byte 3.
If the 82C881 is the initiator of a PCI bus cycle, it drives C/BE[3:0]#. When it is
the target, it samples C/BE[3:0]#.
Even Parity: The 82C881 calculates PAR for both the address and data phases
of PCI cycles. PAR is valid one PCI clock after the associated address or data
phase, but may or may not be valid for subsequent clocks. It is calculated based
on 36 bits - AD[31:0] plus C/BE[3:0]#. "Even" parity means that the sum of the 36
bit values plus PAR is always an even number, even if one or more bits of
C/BE[3:0]# indicate invalid data.
Cycle Frame: This signal is driven by the current PCI bus master to indicate the
beginning and duration of an access. The master asserts FRAME# at the
beginning of a bus cycle, sustains the assertion during data transfers, and then
negates FRAME# in the final data phase.
FRAME# is an input when the 82C881 is the target and an output when it is the
FRAME# is tristated from the leading edge of RESET# and remains tristated until
driven as either a master or slave by the 82C881.
Revision: 1.0
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