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PDF TC7109 Data sheet ( Hoja de datos )
| Número de pieza | TC7109 | |
| Descripción | 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS | |
| Fabricantes | TelCom | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TC7109 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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1
TC7109
TC7109A
12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
FEATURES
s Zero-Integrator Cycle for Fast Recovery From
Input Overloads
s Eliminates Cross -Talk in Multiplexed Systems
s 12-Bit Plus Sign Integrating A/D Converter With
Overrange Indication
s Sign Magnitude Coding Format
s True Differential Signal Input and Differential
Reference Input
s Low Noise ............................................ 15 µVP-P Typ
s Input Current .............................................. 1 pA Typ
s No Zero Adjustment Needed
s TTL-Compatible, Byte-Organized Tri-State
Outputs
s UART Handshake Mode for Simple Serial Data
Transmission
ORDERING INFORMATION
PART CODE
A or blank*
TC7109X
Package
Code
Package
Temperature
Range
CKW
44-Pin PQFP
0°C to +70°C
CLW
44-Pin PLCC
0°C to +70°C
CPL
40-Pin Plastic DIP
0°C to +70°C
IJL
40-Pin CerDIP
–25°C to +85°C
* The "A" version has a higher IOUT on the digital lines.
GENERAL DESCRIPTION
The TC7109A is a 12-bit plus sign, CMOS low-power
analog-to-digital converter (ADC). Only eight passive com-
ponents and a crystal are required to form a complete
dual-slope integrating ADC.
The improved VOH source current TC7109A has fea-
tures that make it an attractive per-channel alternative to
analog multiplexing for many data acquisition applica-
tions. These features include typical input bias current of
1pA drift of less than 1µV/°C, input noise typically 15µVP-P,
and auto-zero. True differential input and reference allow
measurement of bridge-type transducers such as load
cells, strain gauges, and temperature transducers.
The TC7109A provides a versatile digital interface. In
the direct mode, chip select and HIGH/LOW byte enables
control parallel bus interface. In the handshake mode, the
TC7109A will operate with industry-standard UARTs in
controlling serial data transmission — ideal for remote
data logging. Control and monitoring of conversion timing
is provided by the RUN/HOLD input and STATUS output.
For applications requiring more resolution, see the
TC500, 15-bit plus sign ADC data sheet.
The TC7109A has improved overrange recovery per-
formance and higher output drive capability than the origi-
nal TC7109. All new (or existing) designs should specify
the TC7109A wherever possible.
2
3
4
5
FUNCTIONAL BLOCK DIAGRAM
REF
CAP +
REF
IN +
37 36
CREF REF
IN –
39
REF
CAP
RINT
–
38 30
BUF3F1
CAZ
AZ 32
CINT
INT
17
INPUT 35 INT
HI
AZ AZ
ZI ZI
DE DE
(–) (+)
BUFFER
–
+
INTEGRATOR
– COMPARATOR
+
COMP
OUT
HIGH-ORDER
BYTE OUTPUTS
LOW-ORDER
BYTE OUTPUTS
3 4 5 6 7 8 9 10 11 12 13 14 15 16
16 THREE-STATE OUTPUTS
14 LATCHES
AZ
33
COMMON
INPUT 34 INT
LO
DE DE
(+) (–)
AZ
DE (±)
ZI
ZI AZ
TC7109A
COMP OUT
TO AZ
10 µA
ANALOG
INT
SECTION
DE (±)
ZI
–
+
CONVERSION
CONTROL
LOGIC
12-BIT COUNTER
LATCH
CLOCK
OSCILLATOR
AND CLOCK
CIRCUITRY
HANDSHAKE
LOGIC
6.2V
18 LBEN
19 HBEN
20 CE/LOAD
29 28
REF V–
OUT
TELCOM SEMICONDUCTOR, INC.
40
V+
2
STATUS
26 22 23 24 25 21
RUN/ OSC OSC OSC BUF MODE
HOLD IN OUT SEL OSC
OUT
27
SEND
1
GND
TC7109/A-7 11/6/96
3-91
6
7
8
1 page  
12-BIT µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
TC7109/A PIN DESCRIPTION
40-Pin PDIP
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Symbol
GND
STATUS
POL
OR
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
TEST
LBEN
19 HBEN
20 CE/LOAD
21 MODE
22 OSC IN
23 OSC OUT
24 OSC SEL
25 BUF OSC OUT
26 RUN/HOLD
TELCOM SEMICONDUCTOR, INC.
Description
Digital ground, 0V, ground return for all digital logic.
Output HIGH during integrate and deintegrate until data is latched. Output LOW
when analog section is in auto-zero or zero-integrator configuration.
Polarity — High for positive input.
Overrange — High if overranged.
Bit 12 (Most Significant Bit)
Bit 11
Bit 10
Bit 9
Bit 8 All Three-State Data Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 (Least Significant Bit)
Input High — Normal operation. Input LOW — Forces all bit outputs HIGH.
Note: This input is used for test purposes only.
Low-Byte Enable — With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW,
taking this pin LOW activates low-order byte outputs, B1–B8. With MODE (Pin 21)
HIGH, this pin serves as low-byte flag output used in handshake mode. See
Figures 7, 8, and 9.
High-Byte Enable — With MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW,
taking this pin LOW activates high-order byte outputs, B9–B12, POL, OR. With
MODE (Pin 21) HIGH, this pin serves as high-byte flag output used in handshake
mode. See Figures 7, 8, and 9.
Chip Enable/Load — With MODE (Pin 21) LOW, CE/LOAD serves as a master
output enable. When HIGH, B1–B12, POL, OR outputs are disabled. When
MODE (Pin 21) is HIGH, a load strobe is used in handshake mode. See Figure 7,
8, and 9.
Input LOW — Direct output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and
LBEN (Pin 18) act as inputs directly controlling byte outputs.
Input Pulsed HIGH — Causes immediate entry into handshake mode and output
of data as in Figure 9.
Input HIGH — Enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18)
as outputs, handshake mode will be entered and data output as in Figures 7 and
8 at conversions completion.
Oscillator Input
Oscillator Output
Oscillator Select — Input HIGH configures OSC IN, OSC OUT, BUF OSC OUT as
RC oscillator — clock will be same phase and duty cycle as BUF OSC OUT. Input
LOW configures OSC IN, OSC OUT for crystal oscillator — clock frequency will
be 1/58 of frequency at BUF OSC OUT.
Buffered Oscillator Output
Input HIGH — Conversions continuously performed every 8192 clock pulses.
Input LOW — Conversion in progress completed; converter will stop in auto-zero
seven counts before integrate.
2
3
4
5
6
7
8
3-95
5 Page 
12-BIT µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
Handshake Mode
An alternative means of interfacing the TC7109A to
digital systems is provided when the handshake output
mode of the TC7109A becomes active in controlling the
flow of data instead of passively responding to chip and
byte enable inputs. This mode allows a direct interface
between the TC7109A and industry-standard UARTs with
no external logic required. The TC7109A provides all the
control and flag signals necessary to sequence the two
bytes of data into the UART and initiate their transmission
in serial form when triggered into the handshake mode.
The cost of designing remote data acquisition stations is
reduced using serial data transmission to minimize the
number of lines to the central controlling processor.
The MODE input controls the handshake mode. When
the MODE input is held HIGH, the TC7109A enters the
handshake mode after new data has been stored in the
output latches at the end of every conversion performed
(see Figures 7 and 8). Entry into the handshake mode may
be triggered on demand by the MODE input. At any time
during the conversion cycle, the LOW-to-HIGH transition of
a short pulse at the MODE input will cause immediate entry
into the handshake mode. If this pulse occurs while new
data is being stored, the entry into handshake mode is
delayed until the data is stable. The MODE input is ignored
in the handshake mode, and until the converter completes
the output cycle and clears the handshake mode, data
updating will be inhibited (see Figure 9).
When the MODE input is HIGH or when the converter
enters the handshake mode, the chip and byte enable
inputs become TTL-compatible outputs which provide the
output cycle control signals (see Figures 7, 8 and 9).
The SEND input is used by the converter as an indica-
tion of the ability of the receiving device (such as a UART)
to accept data in the handshake mode. The sequence of
the output cycle with SEND held HIGH is shown in Figure
7. The handshake mode (internal MODE HIGH) is entered
after the data latch pulse (the CE/LOAD, LBEN and HBEN
terminals are active as outputs since MODE remains HIGH).
The HIGH level at the SEND input is sensed on the
same HIGH-to-LOW internal clock edge. On the next LOW-
to-HIGH internal clock edge, the high-order byte (bits 9
through 12, POL, and OR) outputs are enabled and the CE/
LOAD and the HBEN outputs assume a LOW level. The
CE/LOAD output remains LOW for one full internal clock
period only; the data outputs remain active for 1-1/2 inter-
nal clock periods; and the high-byte enable remains LOW
for 2 clock periods. The CE/LOAD output LOW level or
LOW-to-HIGH edge may be used as a synchronizing sig-
nal to ensure valid data, and the byte enable as an output
may be used as a byte identification flag. With SEND
remaining HIGH the converter completes the output cycle
using CE/LOAD and LBEN while the low-order byte out-
puts (bits 1 through 8) are activated. When both bytes are
sent, the handshake mode is terminated. The typical UART
interfacing timing is shown in Figure 8. The SEND input is
used to delay portions of the sequence, or handshake, to
ensure correct data transfer. This timing diagram shows an
industry-standard HD6403 or CDP1854 CMOS UART to
interface to serial data channels. The SEND input to the
TC7109A is driven by the TBRE (Transmitter Buffer Regis-
ter Empty) output of the UART, and the CE/LOAD input of
the TC7109A drives the TBRL (Transmitter Buffer Register
Load) input to the UART. The eight transmitter buffer regis-
ter inputs accept the parallel data outputs. With the UART
transmitter buffer register empty, the SEND input will be
HIGH when the handshake mode is entered after new data
is stored. The high-order byte outputs become active and
the CE/LOAD and HBEN inputs will go LOW after SEND is
sensed. When CE/LOAD goes HIGH at the end of one
clock period, the high-order byte data is clocked into the
UART transmitter buffer register. The UART TBRE output
will go LOW, which halts the output cycle with the HBEN
output LOW, and the high-order byte outputs active. When
the UART has transferred the data to the transmitter regis-
ter and cleared the transmitter buffer register, the TBRE
returns HIGH. The high-order byte outputs are disabled on
the next TC7109A internal clock HIGH-to-LOW edge, and
one-half internal clock later, the HBEN output returns HIGH.
The CE/LOAD and LBEN outputs go LOW at the same
time as the low-order byte outputs become active. When
the CE/LOAD returns HIGH at the end of one clock period,
the low-order data is clocked into the UART transmitter
buffer register, and TBRE again goes LOW. The next
TC7109A internal clock HIGH-to-LOW edge will sense
when TBRE returns to a HIGH, disabling the data inputs.
One-half internal clock later, the handshake mode is cleared,
and the CE/LOAD, HBEN and LBEN terminals return
HIGH and stay active, if MODE still remains HIGH.
Handshake output sequences may be performed on
demand by triggering the converter into handshake mode
with a LOW-to-HIGH edge on the MODE input. A hand-
shake output sequence triggered is shown in Figure 9. The
SEND input is LOW when the converter enters handshake
mode. The whole output sequence is controlled by the
SEND input, and the sequence for the first (high order) byte
is similar to the sequence for the second byte.
Figure 9 also shows that the output sequence can take
longer than a conversion cycle. New data will not be latched
when the handshake mode is still in progress and is there-
fore lost.
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3
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8
TELCOM SEMICONDUCTOR, INC.
3-101
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet TC7109.PDF ] | |
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