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PDF TC71 Data sheet ( Hoja de datos )

Número de pieza TC71
Descripción SYSTEM SUPERVISOR
Fabricantes TelCom 
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1
TC70/71
MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY
MONITOR, WATCHDOG AND BATTERY BACKUP
2
FEATURES
s Maximum Functional Integration: Precision Power
Supply Monitor, Watchdog Timer, External RESET
Override, Threshold Detector and Battery Backup
Controller in an 8-Pin Package
s Generates Power-on RESET and Guards Against
Unstable Processor Operation Resulting from
Power "Brown-out"
s Automatically Halts and Restarts an Out-of-
Control Microprocessor
s Output Can be Wire-ORed, or Hooked to Manual
RESET Pushbutton Switch
s Watchdog Disable Pin for Easier Prototyping
(TC70)
s Voltage Monitor for Power Fail or Low Battery
Warning (TC71)
s Available in 8-Pin Plastic DIP or 8-Pin SOIC
Packages
s Cost Effective
TYPICAL APPLICATIONS
s All Microprocessor-based Systems
s Test Equipment
s Instrumentation
s Set-Top Boxes
FUNCTIONAL BLOCK DIAGRAM
VCC
CEI
(TC70)
VBATT
BATTERY
BACK-UP
CONTROL
VCCO
CEO
(TC70)
PF
(TC71)
WDD
(TC70)
GND
TDI
(TC71)
WATCHDOG
TIMER
VREF1
V
DETECTOR
VREF3
VREF2
DELAY
TIMER
TC70/71
RS
TDO
(TC71)
GENERAL DESCRIPTION
The TC70/71 is a fully-integrated power supply monitor,
watchdog and battery backup circuit in a space-saving
8-pin package.
When power is initially applied, the TC70/71 holds the
processor in its reset state for a minimum of 500msec after
VCC is in tolerance to ensure stable system start-up. After
start-up, processor sanity is monitored by the on-board
watchdog circuit. The processor must provide periodic high-
to-low level transitions to the TC70/71 to verify proper
execution. Should the processor fail to supply this signal
within the specified timeout period, an out-of-control proces-
sor is indicated and the TC70/71 issues a momentary
processor reset as a result. The TC70 also features a
watchdog disable pin to facilitate system test and debug.
The output of the TC70/71 can be wire-ORed to a push-
button switch (or electronic signal) to reset the processor.
When connected to a push-button switch, the TC70/71
provides contact debounce.
The integrated battery backup circuit on-board the TC70/
71 converts CMOS RAM into nonvolatile memory by first
write-protecting, then switching the VCC line of the RAM over
to an external battery.
The TC71 incorporates an additional 1.3V threshold
detector for power fail warning, low battery detection or to
monitor power supply voltages other than +5V.
3
4
5
ORDERING INFORMATION
Part No.
TC70COA
TC70CPA
TC70EOA
TC70EPA
TC71COA
TC71CPA
TC71EOA
TC71EPA
Package
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
Temp. Range
0°C to +70°C
0°C to +70°C
– 40°C to +85°C
– 40°C to +85°C
0°C to +70°C
0°C to +70°C
– 40°C to +85°C
– 40°C to +85°C
6
7
PIN CONFIGURATIONS (DIP and SOIC)
VCCO
VCC
1
2
GND 3
CEI 4
TC70
8 VBATT
7 RS
VCCO
VCC
1
2
6 WDD
GND 3
5 CEO
TDI 4
TC71
8 VBATT
7 RS
6 PF
5 TDO
8
TELCOM SEMICONDUCTOR, INC.
TC70/71-1 11/18/96
5-7

1 page




TC71 pdf
MICROMASTER™ – SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP
1
TC70
TC71
Resistor Value Selection
The values of R1 and R2 must be chosen to ensure a
valid low strobe level (VSTL) on RS when the processor I/O
line is low. The use of 10k, ±5% tolerance resistors are
recommended. These values result in a nominal strobe level
of 2.83V on RS (min/max of 2.43V/3.24V, assuming
VDD = 5.0V ±10%). Other resistor values can be used, so
long as the additive tolerances of the power supply and
resistor values result in a strobe that falls within VSTH and
VSTL under all additive tolerance conditions.
External Override Reset Control
A built-in debounce circuit allows a pushbutton switch
(or other electronic reset signal) to be wire-ORed to RS as
an external reset override (Figure 4). The external reset
signal is required to be an active low signal of at least
20msec in duration. Internally, this input is timed to provide
a minimum reset pulse width output of 500msec.
Threshold Detector
The TC71 issues a low-true output on the TDO pin any
time the TDI pin is less than 1.3V and VCC is greater than
VBATT. The voltage to be monitored is connected to the TDI
input through a simple resistor divider. The threshold detec-
tor can be used to generate an early power fail warning if the
unregulated DC input to the +5V regulator is available for
monitoring.
Integrated Battery Backup (TC70)
The CEO line (TC70) drives the CE input of a CMOS
RAM or other device to be battery-backed. CEO follows CEI
as long as VCC is greater than 4.5V nominal. If VCC falls
below 4.5V nominal, CEO is driven to the potential of VCCO
thus write protecting the RAM and preventing accidental
data corruption during power up and power down. The
battery switchover circuit compares VCC to the VBATT input
and connects VCCO to whichever is higher. Switchover
(VSW) occurs when VCC is 10mV below VBATT as VCC falls,
and when VCC is 10mV more than VBATT as VCC rises. The
battery switchover comparator has 20mV of hysteresis to
prevent switch chattering if VCC falls very slowly.
2
Integrated Battery Backup (TC71)
The TC71 differs from the TC70 in that it has a Power
Fail (PF) output instead of a gated chip enable (CEI, CEO).
PF must be externally gated with the decode for the CMOS
RAM or other device to be battery-backed. (Many CMOS
RAMs have both CE and CE enables. In this case, the PF
output can be connected directly to the CE input of the RAM).
PF is high as long as VCC is greater than 4.5V nominal.
When VCC falls below 4.5V nominal, PF is driven low.
Battery switchover for the TC71 is otherwise identical to that
of the TC70.
Supply Monitor Noise Sensitivity
The TC70/71 is optimized for fast response to negative-
going changes in VDD. Systems with an inordinate amount
of electrical noise on VDD (such as systems using relays),
may require a 0.1µF bypass capacitor to reduce detection
sensitivity. This capacitor should be installed as close to the
TC70/71 as possible to keep the capacitor lead length short.
3
4
5
TYPICAL APPLICATIONS
Figure 1 shows a full feature implementation of the
TC70; Figure 2 shows the TC71. Resistors R1 and R2 of
Figure 2 set the trip point voltage for the early power fail
warning circuit using the TC71 threshold detector.
6
WDD
VCCO
+5V VCC CEO
VCC
CE
CMOS
RAM
TC70
VBATT
+3V LI
BATTERY
GND
CEI
RS
+5V
R1
10K
ADDRESS
DECODER
R2
13K
RESET
Figure 1. TC70 Typical Application
TELCOM SEMICONDUCTOR, INC.
ADDRESS
I/O
RESET
PROCESSOR
7
8
5-11

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