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PDF UC2825B Data sheet ( Hoja de datos )

Número de pieza UC2825B
Descripción High Speed PWM Controller
Fabricantes Unitrode 
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UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
High Speed PWM Controller
FEATURES
• Improved versions of the
UC3823/UC3825 PWMs
• Compatible with Voltage or
Current-Mode Topologies
• Practical Operation at Switching
Frequencies to 1MHz
• 50ns Propagation Delay to Output
• High Current Dual Totem Pole
Outputs (2A Peak)
• Trimmed Oscillator Discharge
Current
• Low 100µA Startup Current
• Pulse-by-Pulse Current Limiting
Comparator
• Latched Overcurrent Comparator
With Full Cycle Restart
BLOCK DIAGRAM
DESCRIPTION
The UC3823A & B and the UC3825A & B family of PWM control ICs are im-
proved versions of the standard UC3823 & UC3825 family. Performance en-
hancements have been made to several of the circuit blocks. Error amplifier gain
bandwidth product is 12MHz while input offset voltage is 2mV. Current limit
threshold is guaranteed to a tolerance of 5%. Oscillator discharge current is spec-
ified at 10mA for accurate dead time control. Frequency accuracy is improved
to 6%. Startup supply current, typically 100µA, is ideal for off-line applications.
The output drivers are redesigned to actively sink current during UVLO at no
expense to the startup current specification. In addition each output is capable
of 2A peak currents during transitions.
Functional improvements have also been implemented in this family. The
UC3825 shutdown comparator is now a high-speed overcurrent comparator with
a threshold of 1.2V. The overcurrent comparator sets a latch that ensures full
discharge of the soft start capacitor before allowing a restart. While the fault latch
is set, the outputs are in the low state. In the event of continuous faults, the soft
start capacitor is fully charged before discharge to insure that the fault frequency
does not exceed the designed soft start period. The UC3825 Clock pin has be-
come CLK/LEB. This pin combines the functions of clock output and leading
edge blanking adjustment and has been buffered for easier interfacing.
continued
* Note: 1823A,B Version Toggles Q and Q are always low
9/95
UDG-95101

1 page




UC2825B pdf
APPLICATIONS INFORMATION (cont.)
OSCILLATOR (cont.)
Oscillator Frequency vs. RT and CT Curve
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
Maximum Duty Cycle vs RT Curve
UDG-95103
UDG-95104
LEADING EDGE BLANKING
The UC3823A,B/3825A,B performs fixed frequency pulse
width modulation control. The UC3823A,B outputs oper-
ate together at the switching frequency and can vary from
0 to some value less than 100%. The UC3825A,B outputs
are alternately controlled. During every other cycle, one
output will be off. Each output then, switches at one-half
the oscillator frequency, varying in duty cycle from 0 to less
than 50%.
To limit maximum duty cycle, the internal clock pulse
blanks both outputs low during the discharge time of the
oscillator. On the falling edge of the clock, the appropriate
output(s) is driven high. The end of the pulse is controlled
by the PWM comparator, current limit comparator, or the
overcurrent comparator.
Normally the PWM comparator will sense a ramp cross-
ing a control voltage (error amp output) and terminate the
pulse. Leading edge blanking (LEB) causes the PWM
comparator to be ignored for a fixed amount of time after
the start of the pulse. This allows noise inherent with
switched mode power conversion to be rejected. The
PWM ramp input may not require any filtering as result of
leading edge blanking.
To program a Leading Edge Blanking period, connect a
capacitor, C, to CLK/LEB. The discharge time set by C and
the internal 10k resistor will determine the blanked inter-
val. The 10k resistor has a 10% tolerance. For more ac-
curacy, an external 2k 1% resistor, R, can be added, re-
sulting in an equivalent resistance of 1.66k with a tolerance
of 2.4%. The design equation is:
LEB Operational Waveforms
UDG-95105
tLEB = 0.5 • (R | | 10k) • C.
Values of R less than 2k should not be used
Leading edge blanking is also applied to the current limit
comparator. After LEB, if the ILIM pin exceeds the one
volt threshold, the pulse is terminated. The over current
comparator, however, is not blanked. It will catch catas-
trophic over current faults without a blanking delay. Any
time the ILIM pin exceeds 1.2V, the fault latch will be set
and the outputs driven low. For this reason, some noise
filtering may be required on the ILIM pin.
5

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