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PDF XC68341 Data sheet ( Hoja de datos )
| Número de pieza | XC68341 | |
| Descripción | Integrated Processor | |
| Fabricantes | Motorola Semiconductors | |
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Parts Not Suitable for New Designs
For Additional Information
End-Of-Life Product Change Notice
1 page  
6. Additional Notes on CPU Space Address Encoding
On page 3-31, Figure 3-16, the BKPT field for the Breakpoint Acknowledge address encoding is on bits 4-2,
and the T bit is on bit 1. The Interrupt Acknowledge LEVEL field is on bits 3-1.
7. Breakpoints
On page 3-31, the last paragraph implies that either a software breakpoint (BKPT instruction) or hardware
breakpoint can be used to insert an instruction. As noted in the following paragraphs, only a software
breakpoint can be used to insert an instruction on the breakpoint acknowledge cycle.
8. Interrupt Latency
Add to the Interrupt Acknowledge Bus Cycles section on page 3-36: Interrupt latency from IRQx assert to
prefetch of the first instruction in the interrupt handler is about 37 clocks + worst case instruction length in
clocks (using 2-clock memory and autovector termination). From the instruction timing tables, this gives 37+71
(DIVS.L with worst-case <fea>) = 108 clocks worst case interrupt latency time. For applications requiring
shorter interrupt response time the latency can be reduced by using simpler addressing modes and/or avoiding
use of longer instructions (specifically DIVS.L, DIVU.L, MUL.L).
9. Interrupt Hold Time and Spurious Interrupts
Add to the Interrupt Acknowledge Bus Cycles section on page 3-36: Level sensitive interrupts must remain
asserted until the corresponding IACK cycle; otherwise, a spurious interrupt exception may result or the inter-
rupt may be ignored entirely. This is also true for level sensitive external interrupts which are autovectored us-
ing either the AVEC signal or the AVEC register, since the SIM will not respond to an interrupt arbitration cycle
on the IMB if the external interrupt at that level has been removed. External interrupts configured as edge sen-
sitive only have to be held a minimum of 1.5 clocks - see section 4.3.5.8 PROGRAMMABLE INTERRUPT
REGISTER (PIR).
Note that the level 7 interrupt is also level sensitive, and must be held until a level 7 IACK begins. The level 7
interrupt is unique in that it cannot be masked - another level 7 interrupt exception can be created after the
IACK cycle by negating IRQ7 and reasserting, even though the interrupt mask level in the SR is now set to
level 7.
10. Typos in IACK Cycle Timing Waveforms
On page 3-38, Figure 3-21, the text “VECTOR FROM 16-BIT PORT” should be on D7-D0, and “VECTOR
FROM 8-BIT PORT” should be on D15-D8. The responding device returns the vector number on the least sig-
nificant byte of the data port.
11. Additional Note on Internal Autovector Operation
Add to the Autovector Interrupt Acknowledge Cycle section on page 3-38: If an external interrupt level is
autovectored either by the AVEC register programming or the external AVEC signal, an external IACK will be
started and terminated internally. The interrupting device should not respond to this IACK in any way, or the
resulting operation is undefined.
12. Additional Notes on Retry Termination
On page 3-42, Table 3-4: When HALT and BERR are asserted together in case #5 to force a retry of the current
bus cycle, relative timing of HALT and BERR must be controlled to avoid inadvertently causing bus error ter-
MOTOROLA
MC68341 USER’S MANUAL ADDENDUM
4
5 Page 
A VCO overshoot can occur when increasing the operating frequency by changing the Y bits in the SYNCR
register. The effects of this overshoot can be controlled by following this procedure:
1. Write the X bit to zero. This will reduce the previous frequency by one half.
2. Write the Y bits to the desired frequency divided by 2.
3. After the VCO lock has occurred, write the X bit to one. This changes the
clock frequency to the desired frequency.
Steps 1 and 2 may be combined.
30. RCCR Initialization
Add to the RCCR description on page 4-41: the RCCR register is unaffected by a processor reset, and contains
an arbitrary value on initial powerup of the RTC. Calibration software should clear the RCCR register before
beginning the calibration process, since RTC operation with an invalid RCDx value is undefined. RCCR[7] is
reserved - on current silicon it always reads 0, and should always be written 0.
31. RCCR Typos
On page 4-42, delete the first description for RCD4-RCD0 near the top of the page.
32. MONTH Register Range
The valid range for the MONTH register on page 4-43 is 1-12, with “1” corresponding to January and “12” cor-
responding to December.
33. SIM41 Example Code
On page 4-49, about mid-page, change “MOVEQ #8-1,D0” to “MOVEQ #16-1,D0” to initialize all 8 chip se-
lects.
34. Bus Error Stack Frame
On page 5-61, in the next-to-last paragraph, delete “(the internal transfer count register is located at SP+$10
and the SSW is located at SP+12)”. The stack space allocation is the same for both faults - the location of the
internal count register and SSW remains the same. The only difference is that the faulted instruction program
counter location SP+10 and SP+12 will contain invalid data. To tell the difference between the two stack
frames, look at the first nibble of the faulted exception format vector word located at SP+$E - it will be $0 for
the four-word frame, and $2 for the six-word frame.
35. DSO Timing
On page 5-71, Figure 5-23, DSO transitions one clock later than shown.
36. Typo on BDM RSREG Command
On page 5-77, Section 5.6.2.8.6, RSREG register bit #8 should be a “1”.
37. IPIPE Timing
On page 5-88, Figure 5-29 shows the third IPIPE assertion low lasting for 1.5 CLKs - it actually asserts for an
additional 0.5 CLKs. IPIPE transitions occur after the falling edge of CLKOUT.
MOTOROLA
MC68341 USER’S MANUAL ADDENDUM
10
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