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PDF DS1744 Data sheet ( Hoja de datos )

Número de pieza DS1744
Descripción Y2K-Compliant / Nonvolatile Timekeeping RAMs
Fabricantes Dallas 
Logotipo Dallas Logotipo



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No Preview Available ! DS1744 Hoja de datos, Descripción, Manual

DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
§ Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source
§ Clock Registers are Accessed Identically to
the Static RAM. These Registers are Resident
in the Eight Top RAM Locations.
§ Century Byte Register (i.e., Y2K Compliant)
§ Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
§ BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap-Year Compensation Valid
Up to the Year 2100
§ Battery Voltage-Level Indicator Flag
§ Power-Fail Write Protection Allows for ±10%
VCC Power-Supply Tolerance
§ Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
§ DIP Module Only
Standard JEDEC Byte-Wide 32k x 8 Static
RAM Pinout
§ PowerCapÒ Module Board Only
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174xP Timekeeping RAM
§ Also Available in Industrial Temperature
Range: -40°C to +85°C
PIN CONFIGURATIONS
TOP VIEW
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 Dallas 28
2 Semiconductor 27
3 DS1744 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
PDIP Module
(700-mil Extended)
N.C.
N.C.
N.C.
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1 34
2
Dallas
33
3
4
5
Semiconductor
DS1744P
32
31
30
6 29
7 28
8 27
9 26
10 25
11 24
12 23
13 22
14 21
15 20
16
17
X1 GND VBAT X2
19
18
PowerCap Module Board
(Uses DS9034PCX PowerCap)
N.C.
N.C.
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
PowerCap is a registered trademark of Dallas Semiconductor.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS1744 pdf
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
ADDRESS
B7
B6
B5
DATA
B4 B3
7FFFF
10 Year
7FFFE
X
X
X 10 Month
7FFFD
X
X
10 Date
7FFFC
BF
FT
X
X
X
7FFFB
7FFFA
X
X
X 10 Hour
10 Minutes
7FFF9
OSC
10 Seconds
7FFF8
W
R
10 Century
B2 B1
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
B0 FUNCTION RANGE
Year
00-99
Month
01-12
Date
01-31
Day 01-07
Hour
Minutes
00-23
00-59
Seconds 00-59
Century 00-39
OSC = Stop Bit
R = Read Bit
FT = Frequency Test
W = Write Bit
X = See Note
BF = Battery Flag
NOTE: All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and
CE (chip enable) is low. The device architecture allows ripple-through access to any of the address
locations in the NV SRAM. Valid data is available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable access
time (tOEA). The state of the DQ pins is controlled by CE and OE . If the outputs are activated before tAA,
the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and
OE remain valid, output data remains valid for output-data hold time (tOH) but then goes indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal is high during a write cycle. However, OE can be active provided that
care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the
data bus can become active with read data defined by the address inputs. A low transition on WE then
disables the output tWEZ after WE goes active.
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DS1744 arduino
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