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Número de pieza | DS1746 | |
Descripción | Y2K-Compliant / Nonvolatile Timekeeping RAMs | |
Fabricantes | Dallas | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de DS1746 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
No Preview Available ! DS1746/DS1746P
Y2KC Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identical to the
static RAM. These registers are resident in the
eight top RAM locations.
Century byte register; ie., Y2K compliant
Totally nonvolatile with over 10 years of
operation in the absence of power
BCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year
2100
Battery voltage level indicator flag
Power-fail write protection allows for ±10%
VCC power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
DIP Module only
- Standard JEDEC bytewide 128k x 8 static
RAM pinout
PowerCap Module Board only
- Surface mountable package for direct
connection to PowerCap containing
battery and crystal
- Replaceable battery (PowerCap)
- Power-On Reset Output
- Pin for pin compatible with other densities
of DS174XP Timekeeping RAM
PIN ASSIGNMENT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 NC
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
32-Pin Encapsulated Package
NC
A15
A16
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1 34
2 33
3 32
4 31
5 30
6 29
7 28
8 27
9 26
10 25
11 24
12 23
13 22
14 21
15
16
X1 GND VBAT X2
20
19
17 18
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1 of 18
022101
1 page DS1746 REGISTER MAP Table 2
ADDRESS B7
B6
B5
DATA
B4 B3
1FFFF
10 YEAR
1FFFE X
X
X 10 MO
1FFFD X
X
10 DATE
1FFFC BF FT
X
X
X
1FFFB X
X
10 HOUR
1FFFA X
10 MINUTES
1FFF9 OSC
10 SECONDS
1FFF8 W
R 10 CENTURY
B2 B1
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CENTURY
OSC = STOP BIT
W = WRITE BIT
R = READ BIT
X = SEE NOTE BELOW
DS1746/DS1746P
B0 FUNCTION/RANGE
YEAR
00-99
MONTH 01-12
DATE
01-31
DAY
01-07
HOUR
00-23
MINUTES 00-59
SECONDS 00-59
CENTURY 00-39
FT = FREQUENCY TEST
BF = BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1746 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times
and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output
enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the
outputs are activated before tAA , the data lines are driven to an intermediate state until tAA . If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1746 is in the write mode whenever WE , and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE , or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDS afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to
WE transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the output tWEZ after WE goes active.
5 of 18
5 Page DS1746/DS1746P
WRITE CYCLE TIMING DIAGRAM, WRITE ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CHIP ENABLE CONTROLLED
11 of 18
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet DS1746.PDF ] |
Número de pieza | Descripción | Fabricantes |
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