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PDF CX11656 Data sheet ( Hoja de datos )

Número de pieza CX11656
Descripción Home Networking Physical Layer Device
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No Preview Available ! CX11656 Hoja de datos, Descripción, Manual

CX11656
HomePlug 1.0 PHY
Home Networking Physical
Layer Device with Integrated
Analog Front End Circuitry
Data Sheet (Preliminary)
Conexant Proprietary Information
Conexant Confidential Information
Dissemination, disclosure, or use of this information is not permitted
without the written permission of Conexant Systems, Inc.
Doc. No. 102069A
August 19, 2002

1 page




CX11656 pdf
CX11656 HomePlug 1.0 PHY Data Sheet
Figures
Figure 1-1. CX11656 HomePlug 1.0 PHY Simplified Hardware Interface..........................................................................1-1
Figure 1-2. CX11656 HomePlug 1.0 PHY Functional Block Diagram................................................................................1-2
Figure 2-1. CX11656 PHY Hardware Interface Signals - 144-Pin LQFP ............................................................................2-2
Figure 2-2. CX11656 PHY Pin Signals - 144-Pin LQFP ....................................................................................................2-3
Figure 3-1. CX11656 PHY Block Diagram ........................................................................................................................3-1
Figure 3-2. MII Data Interface with MDI Control ..............................................................................................................3-2
Figure 3-3. MII TX Waveform ..........................................................................................................................................3-3
Figure 3-4. MII RX Waveform..........................................................................................................................................3-4
Figure 3-5. MII TX with Collision Based on RX Activity ....................................................................................................3-4
Figure 3-6. MII Receive Timing........................................................................................................................................3-5
Figure 3-7. MII Transmit Timing ......................................................................................................................................3-5
Figure 3-8. MII Flow Control Overview, Part 1 .................................................................................................................3-7
Figure 3-9. MII Flow Control Overview, Part 2 .................................................................................................................3-7
Figure 3-10. Partition of Serial Bit Stream to Nibble Stream ............................................................................................3-8
Figure 3-11. MDI Receive Timing ....................................................................................................................................3-9
Figure 3-12. MDI Transmit Timing...................................................................................................................................3-9
Figure 3-13. MDI Frame Structure .................................................................................................................................3-10
Figure 3-14. GPSI Data Interface with SPI Control.........................................................................................................3-12
Figure 3-15. GPSI Flow Control .....................................................................................................................................3-13
Figure 3-16. GPSI Transmit Timing ...............................................................................................................................3-13
Figure 3-17. GPSI Receive Timing .................................................................................................................................3-13
Figure 3-18. SPI Slave Port Timing................................................................................................................................3-16
Figure 3-19. AFE TX and RX Activity ..............................................................................................................................3-17
Figure 3-20. AFE Clock Waveforms................................................................................................................................3-17
Figure 3-21. AFE Transmit Timing Diagram ...................................................................................................................3-18
Figure 3-22. AFE Receive Timing Diagram .....................................................................................................................3-18
Figure 3-23. SPI Master Interface Signal Timing Diagram .............................................................................................3-21
Figure 4-1. Package Dimensions - 144-Pin LQFP.............................................................................................................4-1
Figure 5-1. Ethernet Router Application Block Diagram ...................................................................................................5-1
Figure 5-2. USB Application Block Diagram .....................................................................................................................5-2
Figure 5-3. Embedded Application Block Diagram ...........................................................................................................5-3
102069A
Conexant Proprietary and Confidential Information
v

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CX11656 arduino
CX11656 HomePlug 1.0 PHY Data Sheet
2. Hardware Interface
2.1 CX11656 PHY Hardware Interface Signals
The CX11656 PHY hardware interface signals are shown in Figure 2-1.
CX11656 PHY pin signals are shown in Figure 2-2 and are listed in Table 2-1.
CX11656 PHY hardware interface signals are defined in Table 2-2.
102069A
Conexant Proprietary and Confidential Information
2-1

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