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PDF DM86LS62 Data sheet ( Hoja de datos )

Número de pieza DM86LS62
Descripción Dual Rank 8-Bit TRI-STATE Shift Register
Fabricantes National 
Logotipo National Logotipo



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No Preview Available ! DM86LS62 Hoja de datos, Descripción, Manual

August 1991
DM74LS962 (DM86LS62)
Dual Rank 8-Bit TRI-STATE Shift Register
General Description
These circuits are TRI-STATE edge-triggered 8-bit I O reg-
isters in parallel with 8-bit serial shift registers which are
capable of operating in any of the following modes parallel
load from I O pins to register ‘‘A’’ parallel transfer down
from register ‘‘A’’ to serial shift register ‘‘B’’ parallel transfer
up from shift register ‘‘B’’ to register ‘‘A’’ serial shift of regis-
ter ‘‘B’’ or exchange data between register ‘‘A’’ and shift
register ‘‘B’’ Since the registers are edge-triggered by the
positive transition of the clock the control lines which deter-
mine the mode or operation are completely independent of
the logic level applied to the clock Designed for bus-orient-
ed systems these circuits have their TRI-STATE inputs and
outputs on the same pins
Features
Y Registers are edge-triggered by the positive transition
of the clock
Y All inputs are PNP transistors
Y Input disable dominates over output disable
Y Output high impedance state does not impede any oth-
er mode of operation
Y 8-bit I O pins are TRI-STATE buffers
Y Typical shift frequency is 36 MHz
Y Typical power dissipation is 305 mW
Y All control inputs are active when in an ‘‘L’’ logic state
Y Devices can be cascaded into N-bit word
Connection Diagram
Dual-In-Line Package
Pin Description
DISO Output disable
IS Serial input
DISI Input disable
DISTU Transfer up disable
DISTD Transfer down disable
DISS Shift disable
OS Serial output
CLK Clock
GND Ground
I O 1 I O 8 8-bit I O pins
VCC Supply Voltage
Top View
Order Number DM74LS962N or DM86LS62N
See NS Package Number N18A
TL F 6438 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 6438
RRD-B30M105 Printed in U S A

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DM86LS62 pdf
Timing Diagram
TL F 6438 – 3
5

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