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PDF ST10F166 Data sheet ( Hoja de datos )
| Número de pieza | ST10F166 | |
| Descripción | 16-BIT MCU WITH 256K BYTE FLASH MEMORY | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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ST10F166
16-BIT MCU WITH 256K FLASH MEMORY
s High Performance 16-bit CPU with 4-Stage
Pipeline
s 100 ns Instruction Cycle Time at 20 MHz CPU
Clock
s 500 ns Multiplication (16 × 16 bit), 1 µs Division
(32 / 16 bit)
s Enhanced Boolean Bit Manipulation Facilities
s Register-Based Design with Multiple Variable
Register Banks
s Single-Cycle Context Switching Support
s Up to 256 KBytes Linear Address Space for
Code and Data
s 1 KByte On-Chip RAM
s 32 KBytes On-Chip Flash EPROM with Bank
Erase Feature
s Protection-Optional Flash Memory
s Dedicated Flash Control Register with
Operation Lock Mechanism
s 12 V External Flash Programming Voltage
s Flash Program Verify and Erase Verify Modes
s 1000 Flash Program/Erase Cycles guaranteed
s Programmable External Bus Characteristics for
Different Address Ranges
s 8-Bit or 16-Bit External Data Bus
s Multiplexed or Demultiplexed External Address/
Data Buses
s Hold and Hold-Acknowledge Bus Arbitration
Support
s 512 Bytes On-Chip Special Function Register
Area
s Idle and Power Down Modes
s 8-Channel Interrupt-Driven Single-Cycle Data
Transfer Facilities via Peripheral Event
Controller (PEC)
PQFP100
s 16-Priority-Level Interrupt System
s 10-Channel 10-bit A/D Converter with 9.7 µs
Conversion Time (ST10F166)
s 16-Channel Capture/Compare Unit
s Two Multi-Functional General Purpose Timer
Units with 5 Timers
s Two Serial Channels (USARTs)
s Programmable Watchdog Timer
s Up to 76 General Purpose I/O Lines
s Supported by a Wealth of Development Tools
like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers,
Programming Boards
s On-Chip Bootstrap Loader
s 100-Pin Plastic PQFP Package
February 1996
This is preliminary information from SGS-THOMSON. Details are subject to change without notice.
1/62
1 page  
ST10F166
Table 1. Pin Definition and Function
Symbol
P4.0 –
P4.1
XTAL1
XTAL2
BUSACT,
EBC1,
EBC0
VPP
RSTIN
RSTOUT
Pin
Number
16 - 17
16
17
20
19
22
23
24
23
27
28
Input (I)
Output (O)
I/O
O
O
I
O
I
I
I
I
O
Function
Port 4 is a 2-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0A16Least Significant Segment Addr. Line
P4.1A17Most Significant Segment Addr. Line
XTAL1:Input to the oscillator amplifier and input to the internal
clock generator
XTAL2:Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while
leaving XTAL2 unconnected. Minimum and maximum high/low
and rise/fall times specified in the AC Characteristics must be ob-
served.
External Bus Configuration selection inputs. These pins are sam-
pled during reset and select either the single chip mode or one of
the four external bus configurations:
BUSACTEBC1EBC0Mode/Bus Configuration
00 0 8-bit demultiplexed bus
00 1 8-bit multiplexed bus
01 0 16-bit muliplexed bus
01 1 16-bit demultiplexed bus
10 0 Single chip mode
10 1 Reserved.
11 0 Reserved.
11 1 Reserved.
After reset pin EBC1 accepts the programming voltage for the
Flash Memory as an “alternate function”:
Flash Memory Programming Voltage VPP = 12 V.
Reset Input with Schmitt-Trigger characteristics. A low level at
this pin for a specified duration while the oscillator is running re-
sets the ST10R165. An internal pullup resistor permits power-on
reset using only a capacitor connected to VSS.
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
5/62
5 Page 
ST10F166
4 FLASH MEMORY
The ST10F166 provides, in addition to the RAM, 32 k bytes of Electrically Erasable
and reprogram-mable non-volatile (FLASH) memory. This memory is organised as
8K x 32 bit allowing a complete instruction to be read during one instruction fetch cy-
cle. Data values stored can be read as 16 bit operands using all addressing modes of
ST10F166 instruction set.
The FLASH memory is located in segment 0 (0 to 07FFFh) during reset, and thus
contains the reset and interrupt vectors. To provide full flexibility in the use of the
ST10F166, the FLASH memory may be remapped to segment ~ ( 0000 to 17FFFh)
during initialization. This allows the interrupt vector to be programmed from external
memory, while retaining the common routines and constants programmed into the
FLASH memory.
For ease of program updating, the FLASH memory is organised into 4 banks, each of
which may be independently Erased.
Table 2. FLASH memory Bank Organisation
Bank
0
1
2
3
Addresses
(Segment 0)
00000h to 02FFFh
03000h to 05FFFh
06000h to 077FFh
07800h to 07FFFh
Size
(bytes)
12K
12K
6K
2K
11/62
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