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PDF KM6161002B Data sheet ( Hoja de datos )
| Número de pieza | KM6161002B | |
| Descripción | CMOS SRAM | |
| Fabricantes | Samsung | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KM6161002B (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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KM6161002B, KM6161002BI
CMOS SRAM
Document Title
64Kx16 Bit High Speed Static RAM(5.0V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
Revision History
RevNo.
History
Draft Data
Remark
Rev. 0.0
Initial release with Design Target.
Apr. 1st, 1997
Design Target
Rev. 1.0
Release to Preliminary Data Sheet.
1. Replace Design Target to Preliminary.
Jun. 1st, 1997
Preliminary
Rev. 2.0
Release to Final Data Sheet.
2.1. Delete Preliminary
2.2. Delete L-version.
2.3. Delete Data Retention Characteristics and Waveform.
2.4. Add Capacitive load of the test environment in A.C test load
2.5. Change D.C characteristics
Items
Previous spec.
(8/10/12ns part)
Changed spec.
(8/10/12ns part)
Icc
200/190/180mA
200/195/190mA
Isb
30mA
50mA
Feb. 25th, 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of th is
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
February 1998
1 page  
KM6161002B, KM6161002BI
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width( OE High)
Write Pulse Width( OE Low)
UB, LB Valid to End of Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tBW
tWR
tWHZ
tDW
tDH
tOW
KM6161002B-8
Min Max
8-
6-
0-
6-
6-
8-
6-
0-
04
4-
0-
3-
NOTE: The above parameters are also guaranteed at industrial temperature range.
KM6161002B-10
Min Max
10 -
7-
0-
7-
7-
10 -
7-
0-
05
5-
0-
3-
CMOS SRAM
KM6161002B-12
Min Max
12 -
8-
0-
8-
8-
12 -
8-
0-
06
6-
0-
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)
Address
Data Out
tOH
Previous Valid Data
tAA
tRC
Valid Data
-5-
Rev 2.0
February 1998
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet KM6161002B.PDF ] | |
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