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PDF DP8228 Data sheet ( Hoja de datos )

Número de pieza DP8228
Descripción System Controller and Bus Driver
Fabricantes National 
Logotipo National Logotipo



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December 1988
DP8228 DP8228M DP8238 DP8238M
System Controller and Bus Driver
General Description
The DP8228 DP8228M DP8238 DP8238M are system
controller bus drivers contained in a standard 28-pin dual-
in-line package The chip which is fabricated using Schottky
Bipolar technology generates all the read and write control
signals required to directly interface the memory and input
output components of the 8080A microcomputer family The
chip also provides drive and isolation for the bidirectional
data bus of the 8080A microprocessor Data bus isolation
enables the use of slower memory and input output compo-
nents in a system and provides for enhanced system noise
immunity
A user-selected signal-level interrupt vector (RST 7) is pro-
vided by the device for use in the interrupt structure of small
systems that need only one basic vector No additional
components (such as an interrupt instruction port) are re-
quired to use the single interrupt vector in these systems
The devices also generate an Interrupt Acknowledge (INTA)
control signal for each byte of a multibyte CALL instruction
when an interrupt is acknowledged by the 8080A This fea-
ture permits the use of a multilevel priority interrupt structure
in large interrupt-driven systems
Features
Y Single chip system controller and bus driver for 8080A
Microcomputer Systems
Y Allows use of multibyte CALL instructions for Interrupt
Acknowledge
Y Provides user-selected single-level interrupt vector
(RST 7)
Y Provides isolation of data bus
Y Supports a wide variety of system bus structures
Y Reduces system component count
Y DP8238 DP8238M provides advanced Input Output
Write and Memory Write control signals for large sys-
tem timing control
8080A Microcomputer Family Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 6825
TL F 6825 – 1
RRD-B30M105 Printed in U S A

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DP8228 pdf
Functional Pin Definitions (Continued)
tion between the CPU memory and input output devices
for instructions and data transfers A status word (which de-
scribes the current machine cycle) is also outputted on this
data bus during the first microcycle of each machine cycle
(SYNC e logic 1)
System Data (DB7 – DB0) Bus This bus comprises eight
TRI-STATE input output lines that connect to the memory
and input output components of the system The internal
bidirectional bus driver isolates the DB7 – DB0 Data Bus from
the D7 – D0 Data Bus
Status Word Chart
Machine Cycle
Status
Data Bus Bit
Control
Word
D7 D6 D5 D4 D3 D2 D1 D0
Signal
Instruction Fetch
Memory Read
Memory Write
Stack Read
Stack Write
Input Read
Output Write
Interrupt Acknowledge
Halt Acknowledge
Interrupt Acknowledge While Halt
1
2
3
4
5
6
7
8
9
10
1 0 1 0 0 0 1 0 MEMR
1 0 0 0 0 0 1 0 MEMR
0 0 0 0 0 0 0 0 MEMW
1 0 0 0 0 1 1 0 MEMR
0 0 0 0 0 1 0 0 MEMW
01000010
I OR
00010000
I OW
00100011
INTA
1 0 0 0 1 0 1 0 (none)
00101011
INTA
Block and Connection Diagrams
Dual-In-Line Package
TL F 6825 – 6
TL F 6825 – 7
Order Number DP8228J DP8228MJ
DP8228N DP8238J DP8238MJ or
DP8238N
See NS Package Number J28A or N28B
5

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