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PDF UPD61051 Data sheet ( Hoja de datos )

Número de pieza UPD61051
Descripción (UPD61052) MPEG2 Audio / Video Encoder
Fabricantes NEC 
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD61051, 61052
MPEG2 AUDIO/VIDEO ENCODER
The µPD61051 and µPD61052 are LSIs of MPEG audio and video encoding, decoding and transcoding.
The µPD61051 has MPEG2 video encoder, MPEG audio encoding DSP, 32-bit RISC CPU, video input/output unit
which contains a processing filter and a time base corrector (TBC), and MPEG system layer which contains the
multiplexer and de-multiplexer. It combines with 64 M or 128 Mbit SDRAM and it uses. The µPD61052 has a Dolby™
Digital Consumer Encoder in addition to the µPD61051.
The µPD61051, 61052 are the optimal choice for consumer digital video recording replay equipment to process a
MPEG.
FEATURES
Video encode
- Stream standard: MPEG2 video MP@ML, SP@ML standard, MPEG1 standard
- Picture size:
Horizontal: 720, 704, 544, 480, 352 dots/line
Vertical: 480, 240, 576, 288 line/frame
- Single pass variable bit rate (VBR), constant bit rate (CBR) encoding
- Transcoding:
Bit rate conversion, VBR CBR
- Video input/output
Format:
8-bit Y/Cb/Cr 4:2:2 (ITU-R BT.656)
Pre analysis: Film detect, scene changing detect, and motion estimation assist
TBC, VBI data slicer
Audio encoding
- Bit length:
16 bits, 20 bits, 24 bits
- Sampling rate: 32 kHz, 44.1 kHz, 48 kHz
- MPEG1 audio layer 2 standard based
- Dolby Digital Consumer Encoder standard based (Only the µPD61052)
- Elementary stream and PCM audio input/output
MPEG system processing
- Multiplex:
MPEG2-PS, MPEG2-TS, DVD-Video, and DVD-VR
- De-multiplex: MPEG2-PS, MPEG2-TS
- Transcoding: MPEG2 format conversion (MPEG2-TS MPEG2-PS)
- Partial TS generation
Package: 208-pin fine pitch QFP
Power supply: 1200 mW (Typ.)
Power supply voltage: 3.3±0.165 V, 2.5±0.2 V (Internal circuit power)
"Dolby" is a trademark of Dolby Laboratories.
To use the µPD61052, a license from Dolby Laboratories Licensing Corporation is necessary.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15082EJ4V0DS00 (4th edition)
Date Published November 2003 NS CP (K)
Printed in Japan
The mark shows major revised points.
2002

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UPD61051 pdf
PIN CONFIGURATION (TOP VIEW)
208-pin plastic QFP (Fine pitch) (28×28)
µPD61051GD-LML
µPD61051GD-LML-A
µPD61052GD-LML
µPD61052GD-LML-A
VDD2
AMCLK
GND
OALRCK
OABCK
OABD
IALRCK
IABCK
IABD
GND
IVFLD
IVHSYNC
VDD2
IVVSYNC
GND
IVIN0
IVIN1
IVIN2
IVIN3
IVIN4
IVIN5
IVIN6
IVIN7
VDD2
IVCLK
GND
GND
SCLK
PSTOP
PVDD2
PGND
PVDD2
PGND
STCLK
GND
VDD2
GND
GND
VDD3
PWM
GND
IS0
IS1/ISERR
IS2
IS3
IS4
IS5
VDD2
IS6
GND
IS7
ISSYNC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
µPD61051, 61052
156 CMODE1/CSDO
155 CMODE0/CSCLK
154 GND
153 CINT
152 VDD2
151 RESET
150 GND
149 MD15
148 VDD3
147 MD14
146 MD13
145 MD12
144 MD11
143 MD10
142 GND
141 MD9
140 VDD2
139 MD8
138 MD0
137 GND
136 MD1
135 VDD3
134 MD2
133 MD3
132 MD4
131 MD5
130 GND
129 MD6
128 VDD2
127 MD7
126 MDQM
125 MWE
124 GND
123 MCAS
122 VDD3
121 MRAS
120 MCS
119 GND
118 MCLK
117 VDD2
116 MCLKE
115 MA11
114 MA9
113 MA8
112 GND
111 MA7
110 VDD3
109 MA6
108 MA5
107 GND
106 MA4
105 VDD2
Data Sheet S15082EJ4V0DS
5

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UPD61051 arduino
µPD61051, 61052
1.6 Stream Output Interface
This interface outputs MPEG TS/PS stream. When in master mode (MPEG2-TS output with using valid signal),
data output is possible to select 8bits parallel data or serial data mode. In serial mode, data output from OS0.
Active polarity of OSVLD is selected by the port setup register.
Active polarity of OSCLK/OSSTB and OSSYNC are selected by firmware. These are unsettled after the turning on.
Name
OSREQ
OSCLK/OSSTB
OSCLK/OSSTB
OSSYNC
OSVLD/OSRDY
OSVLD/OSRDY
OS7 to OS0/
FA13 to FA6
IO Pin
Number
I 70
O 66
O 66
O 67
O 68
O 68
O 65 to 63,
61, 59 to
56
Function
Stream data request in slave mode
Stream data strobe
After reset, default is active high edge.
Stream data clock
After reset, default is OSSTB.
Stream data synchronization
After reset, default is active high.
Stream data valid
After reset, default is OSRDY.
Stream data ready prepared
After reset, default is active low.
Stream data output
Active
Polarity
L
Remark In this table, means of reset are hardware reset by the RESET pin and ALL RESET of the reset register.
1.7 SDRAM Interface
Name
MA13 to MA0
MD31 to MD0
MCLK
MCKE
MCS
MRAS
MCAS
MWE
MDQM
IO Pin Number
Function
O 104, 103, 115, 102, 114, 113, 111,
109, 108, 106, 101, 99, 97, 95
IO 93 to 89, 87, 85, 83, 72, 75 to 81,
149, 147 to 143, 141, 139, 127,
129, 131 to 134, 136, 138
O 118
O 116
O 120
O 121
O 123
O 125
O 126
Address of row/column
Data
(Built-in 50 kpull up resistor)
Clock
Clock enable
Chip selection
Row address strobe
Column address strobe
Write enable
Data input/output mask enable
Active
Polarity
H
L
L
L
L
L
Data Sheet S15082EJ4V0DS
11

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