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PDF TC58NVG0S3AFT05 Data sheet ( Hoja de datos )
| Número de pieza | TC58NVG0S3AFT05 | |
| Descripción | 1 GBit CMOS NAND EPROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TC58NVG0S3AFT05
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1 GBIT (128M × 8 BITS) CMOS NAND EEPROM
DESCRIPTION
The TC58NVG0S3A is a single 3.3-V 1G-bit (1,107,296,256 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND EEPROM) organized as (2048 + 64) bytes × 64 pages × 1024 blocks. The device has a
2112-byte static registers which allow program and read data to be transferred between the register and the
memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes
+ 4 Kbytes: 2112 bytes × 64 pages).
The TC58NVG0S3A is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed
making the device most suitable for applications such as solid-state file storage, voice recording, image file
memory for still cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
• Powersupply
VCC = 2.7 V to 3.6 V
Memory cell array 2112 × 64K × 8
• Program/Erase Cycles 1E5 Cycles (With ECC)
Register
2112 × 8
• Access time
Page size
2112 bytes
Cell array to register 25 µs max
Block size
(128K + 4K) bytes
Serial Read Cycle
50 ns min
• Modes
• Operating current
Read, Reset, Auto Page Program
Read (50 ns cycle)
10 mA typ.
Auto Block Erase, Status Read
Program (avg.)
10 mA typ.
• Mode control
Erase (avg.)
10 mA typ.
Serial input/output
Standby
50 µA max
Command control
• Package
www.DataSheet4U.comTSOPI48-P-1220-0.50 (Weight: 0.53 g typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
NC
NC
NC
NC
NC
GND
RY / BY
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 NC
47 NC
46 NC
45 NC
44 I/O8
43 I/O7
42 I/O6
41 I/O5
40 NC
39 NC
38 NC
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
I/O1 to I/O8
CE
WE
RE
CLE
ALE
WP
RY / BY
GND
VCC
VSS
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground Input
Power supply
Ground
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AC TEST CONDITIONS
TC58NVG0S3AFT05
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
CONDITION
2.4 V, 0.4 V
3 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
CL (100 pF) + 1 TTL
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = 0 to 70°C, VCC = 2.7 V~3.6 V)
SYMBOL
PARAMETER
MIN
tPROG
N
Average Programming Time
Number of Programming Cycles on Same Page
(per 512 + 16 bytes)
tBERASE
Block Erasing Time
(1) Refer to Application Note (12) toward the end of this document.
TYP.
200
2
MAX
700
2
4
UNIT
µs
ms
NOTES
(1)
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Column Address Change in Read Cycle Timing Diagram (2/2)
TC58NVG0S3AFT05
CLE
CE
WE
tCLS tCLH
tCS tCH
tWC
tCLEA
tCLS tCLH
tCS tCH
tCEA
tRHW
tALH tALS
tALH tALS
ALE
tRC
RE
I/O1
to I/O8
RY/BY
DOUT
A+N
tDS tDH
05h
tDS tDH tDS tDH
CA0 to 7 CA8 to 11
Column address
B
tDS tDH
tIR
E0h
tREA
DOUT DOUT
B B+1
DOUT
B + N’
Page address
P
Column address
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1
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| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet TC58NVG0S3AFT05.PDF ] | |
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