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PDF TC58NS512ADC Data sheet ( Hoja de datos )
| Número de pieza | TC58NS512ADC | |
| Descripción | 512 MBit CMOS NAND EPROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TC58NS512ADC
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M × 8 BITS) CMOS NAND E2PROM (64M BYTE SmartMediaTM)
DESCRIPTION
The TC58NS512A is a single 3.3-V 512-Mbit (553,648,128) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell
array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes:
528 bytes × 32 pages).
The TC58NS512A is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed.
The TC58NS512DC is a SmartMediaTM with ID and each device has 128 bit unique ID number embedded in the
device. This unique ID number is applicable to image files, music files, electronic books, and so on where copyright
protection is required.
The data stored in the TC58NS512ADC needs to comply with the data format standardized by the SSFDC Forum
in order to maintain compatibility with other SmartMediaTM systems.
FEATURES
• Organization
Memory cell allay 528 × 128K × 8
Register
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
• Modes
Read, Reset, Auto Page Program,
Auto Block Erase, Status Read,
• Mode control
Serial input/output, Command control
• Complies with the SmartMediaTM Electrical
Specification and Data Format Specification
issued by the SSFDC Forum
• Power supply
VCC = 3.3 V ± 0.3 V
• Program/Erase Cycles 1E5 cycle (with ECC)
• Access time
Cell array to register 25 µs max
Serial Read Cycle 50 ns min
• Operating current
Read (50 ns cycle) 10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
50 µA max.
• Package
FDC-22A (Weight: 1.8 g typ.)
PIN ASSIGNMENT (TOP VIEW)
VSS CLE ALE WE WP I/O1 I/O2 I/O3 I/O4 VSS VSS
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
PIN NAMES
I/O1 to I/O8
CE
WE
RE
CLE
ALE
WP
RY/BY
GND
LVD
VCC
VSS
VCC CE RE RY/BY GND LVD I/O8 I/O7 I/O6 I/O5 VCC
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground input
Low Voltage Detect
Power supply
Ground
TM
is a trademark of Toshiba Corporation.
1 2004-03-12
1 page  
TC58NS512ADC
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE
delay is less than 30 ns, RY/BY signal stays Ready.
tCEH ≥ 100 ns
* *: VIH or VIL
CE
RE
525 526 527 A
A : 0 to 30 ns → Busy signal is not
output.
RY/BY
Busy
tCRY
PROGRAMMING AND ERASING CHARACTERISTICS (Ta = 0° to 55°C, VCC = 3.3 V ± 0.3 V)
SYMBOL
PARAMETER
MIN
tPROG
tDBSY
Programming Time
Dummy Busy Time for Multi Block
Programming
⎯
⎯
tMBPBSY
N
Multi Block Program Busy Time
Number of Programming Cycles on Same
Page
⎯
⎯
tBERASE
Block Erasing Time
⎯
(1): Refer to Application Note (12) toward the end of this document.
TYP.
200
2
200
⎯
2
MAX
1000
10
1000
3
10
UNIT
µs
µs
µs
ms
NOTES
(1)
5 2004-03-12
5 Page 
Sequential Read (1) Timing Diagram
CLE
TC58NS512ADC
CE
WE
ALE
RE
I/O1
to 00H
RY/BY
A0
to
A9
to
A17
to
A25
A7 A16 A24
Column
Page
address address
NM
tR
N N + 1 N + 2 527
tR
012
Page M
access
Page M + 1
access
: VIH or VIL
Sequential Read (2) Timing Diagram
CLE
527
CE
WE
ALE
RE
I/O1
to 01H
RY/BY
A0
to
A9
to
A17
to
A25
A7 A16 A24
Column
Page
address address
NM
tR
256 + 256 + 256 +
N N+1 N+2
527
tR
012
527
Page M
access
11
Page M + 1
access
: VIH or VIL
2004-03-12
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TC58NS512ADC.PDF ] | |
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