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PDF TC58NVG0S3AFT00 Data sheet ( Hoja de datos )

Número de pieza TC58NVG0S3AFT00
Descripción 1 GBit CMOS NAND EPROM
Fabricantes Toshiba 
Logotipo Toshiba Logotipo



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TC58NVG0S3AFT00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1GBIT (128M u 8BITS) CMOS NAND E2PROM
DESCRIPTION
The TC58NVG0S3A is a single 3.3-V 1G-bit (1,107,296,256 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 1024 blocks.
The device has a 2112-byte static registers which allow program and read data to be transferred
between the register and the memory cell array in 2112-byte increments. The Erase operation is
implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages).
The TC58NVG0S3A is a serial-type memory device which utilizes the I/O pins for both address and data
input / output as well as for command inputs. The Erase and Program operations are automatically
executed making the device most suitable for applications such as solid-state file storage, voice
recording, image file memory for still cameras and other systems which require high-density non-
volatile memory data storage.
FEATURES
x Organization
Memory cell allay 2112 u 64K u 8
Register
2112 u 8
Page size
2112bytes
Block size
(128K  4K) bytes
x Modes
ReadResetAuto Page Program
Auto Block EraseStatus Read
x Mode control
Serial inputoutput
Command control
x Powersupply
VCC 2.7 V to 3.6 V
x Program/Erase Cycles
1E5 Cycles(With ECC)
x Access time
Cell array to register 25 Psmax
Serial Read Cycle
50 ns min
x Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
50 PA max
x Package
TSOP I 48-P-1220-0.50
(Weight : 0.53 g typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
NC
NC
NC
NC
NC
GND
RY/BY
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
www.DataSheet4U.com48 NC
I/O1 to I/O8 I/O port
47 NC
46 NC
CE Chip enable
45 NC
44 I/O8
WE Write enable
43 I/O7
42 I/O6
RE Read enable
41 I/O5
40 NC
39 NC
CLE Command latch enable
38 NC
37 VCC
ALE Address latch enable
36 VSS
35 NC
WP Write protect
34 NC
33 NC
RY / BY
Ready / Busy
32 I/O4
31 I/O3
30 I/O2
GND
Ground Input
29 I/O1
28 NC
VCC
Power supply
27 NC
26 NC
VSS Ground
25 NC
000707EBA1
xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at
the customer’s own risk.
2003-02-25A 1/32
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TC58NVG0S3AFT00 pdf
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AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
TC58NVG0S3AFT00
CONDITION
2.4 V, 0.4 V
3ns
1.5 V, 1.5 V
1.5 V, 1.5 V
CL (100 pF)  1 TTL
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta 0 to 70 , VCC 2.7V ~ 3.6V)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
tPROG
N
Average Programming Time
Number of Programming Cycles on Same Page
(per 512+16 bytes)
 200 700 Ps
 2
tBERASE Block Erasing Time
2
4 ms
(1) Refer to Application Note (12) toward the end of this document.
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NOTES
(1)
2003-02-25A 5/32
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TC58NVG0S3AFT00 arduino
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Column Address Change in Read Cycle Timing Diagram (2/2)
TC58NVG0S3AFT00
CLE
CE
WE
ALE
RE
I/O1
to I/O8
  RY / BY
tCLS tCLH
tCS tCH
tWC
tCLS tCLH
tCS tCH
tCLEA
tCEA
tRHW
tALH tALS
tALH tALS
tRC
DOUT
AN
tDS tDH
05H
tDS tDH tDS tDH
CA0 to CA8 to
7 11
Column address
B
tDS tDH
tIR
E0H
tREA
DOUT DOUT
B B1
DOUT
B  N’
Page address
P
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1
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2003-02-25A 11/32
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