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PDF GE28F128W30BD70 Data sheet ( Hoja de datos )
| Número de pieza | GE28F128W30BD70 | |
| Descripción | (GE28Fxxx Series) Wireless Flash Memory | |
| Fabricantes | Intel | |
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Intel® Wireless Flash Memory (W30)
28F640W30, 28F320W30, 28F128W30
Datasheet
Product Features
■ High Performance Read-While-Write/Erase
— Burst Frequency at 40 MHz
— 70 ns Initial Access Speed
— 25 ns Page-Mode Read Speed
— 20 ns Burst-Mode Read Speed
— Burst and Page Mode in All Blocks and
across All Partition Boundaries
— Burst Suspend Feature
— Enhanced Factory Programming:
3.5 µs per Word Program Time
— Programmable WAIT Signal Polarity
■ Flash Power
— VCC = 1.70 V – 1.90 V
— VCCQ = 2.20 V – 3.30 V
— Standby Current (0.13 µm) = 8 µA (typ.)
— Read Current = 7 mA
(4 word burst, typ.)
■ Flash Software
— 5 µs/9 µs (typ.) Program/Erase Suspend
Latency Time
— Intel® Flash Data Integrator (FDI) and
Common Flash Interface (CFI) Compatible
■ Quality and Reliability
— Operating Temperature:
–40 °C to +85 °C
— 100K Minimum Erase Cycles
— 0.13 µm ETOX™ VIII Process
— 0.18 µm ETOX™ VII Process
■ Flash Architecture
— Multiple 4-Mbit Partitions
— Dual Operation: RWW or RWE
— Parameter Block Size = 4-Kword
— Main block size = 32-Kword
— Top and Bottom Parameter Devices
■ Flash Security
— 128-bit Protection Register: 64 Unique Device
Identifier Bits; 64 User OTP Protection
Register Bits
— Absolute Write Protection with VPP at Ground
— Program and Erase Lockout during Power
Transitions
— Individual and Instantaneous Block Locking/
Unlocking with Lock-Down
■ Density and Packaging
— 0.13 µm: 32-, 64-, and 128-Mbit in VF BGA
Package; 64-, 128-Mbit in QUAD+ Package
— 0.18 µm: 32- and 128-Mbit Densities in VF
BGA Package; 64-Mbit Density in µBGA*
Package
— 56 Active Ball Matrix, 0.75 mm Ball-Pitch
— 16-bit Data Bus
The Intel®Wireless Flash Memory (W30) device combines state-of-the-art Intel® Flash
technology to provide the most versatile memory solution for high performance, low power,
board constraint memory applications. The W30 device offers a multi-partition, dual-operation
flash architecture that enables the device to read from one partition while programming or
erasing in another partition. This Read-While-Write or Read-While-Erase capability makes it
possible to achieve higher data throughput rates as compared to single partition devices,
allowing two processors to interleave code execution because program and erase operations can
now occur as background processes.
The W30 device incorporates a new Enhanced Factory Programming (EFP) mode to improve 12
V factory programming performance. This new feature helps eliminate manufacturing
bottlenecks associated with programming high density flash devices. Compare the EFP program
time of 3.5 µs per word to the standard factory program time of 8.0 µs per word and save
significant factory programming time for improved factory efficiency.
Additionally, the W30 device includes block lock-down and programmable WAIT signal
polarity, and is supported by an array of software tools. All these features make this product a
perfect solution for any demanding memory application.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
290702-010
May 2004
1 page  
28F320W30, 28F640W30, 28F128W30
14.7
14.8
14.9
14.10
Burst Sequence (RCR[7])....................................................................................81
Clock Edge (RCR[6])...........................................................................................83
Burst Wrap (RCR[3]) ...........................................................................................83
Burst Length (RCR[2:0])......................................................................................83
Appendix A Write State Machine .............................................................................................84
Appendix B Common Flash Interface ....................................................................................87
Appendix C Ordering Information ...........................................................................................96
Datasheet
5
5 Page 
Intel® Wireless Flash Memory (W30)
2.0
2.1
Functional Overview
This section provides an overview of the W30 features and architecture.
Overview
The W30 provides Read-While-Write (RWW) and Read-White-Erase (RWE) capability with high-
performance synchronous and asynchronous reads in package-compatible densities with a 16-bit
data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight
4-Kword parameter blocks are located in the parameter partition at either the top or bottom of the
memory map. The rest of the memory array is grouped into 32-Kword main blocks.
The memory architecture for the W30 consists of multiple 4-Mbit partitions, the exact number
depending on device density. By dividing the memory array into partitions, program or erase
operations can take place simultaneously during read operations. Burst reads can traverse partition
boundaries, but user application code is responsible for ensuring that they don’t extend into a
partition that is actively programming or erasing. Although each partition has burst-read, write, and
erase capabilities, simultaneous operation is limited to write or erase in one partition while other
partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An
erase can be suspended to perform a program or read operation within any block, except that which
is erase-suspended. A program operation nested within a suspended erase can subsequently be
suspended to read yet another memory location.
After device power-up or reset, the W30 defaults to asynchronous read configuration. Writing to
the device’s Read Configuration Register (RCR) enables synchronous burst-mode read operation.
In synchronous mode, the CLK input increments an internal burst address generator. CLK also
synchronizes the flash memory with the host CPU and outputs data on every, or on every other,
valid CLK cycle after an initial latency. A programmable WAIT output signals to the CPU when
data from the flash memory device is ready.
In addition to its improved architecture and interface, the W30 incorporates Enhanced Factory
Programming (EFP), a feature that enables fast programming and low-power designs. The EFP
feature provides the fastest currently-available program performance, which can increase a
factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V.
With the 1.8-V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In
addition to voltage flexibility, the dedicated VPP input provides complete data protection when
VPP ≤ VPPLK.
A 128-bit protection register enhances the user’s ability to implement new security techniques and
data protection schemes. Unique flash device identification and fraud-, cloning-, or content-
protection schemes are possible through a combination of factory-programmed and user-OTP data
Datasheet
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