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PDF UC3625 Data sheet ( Hoja de datos )

Número de pieza UC3625
Descripción Brushless DC Motor Controller
Fabricantes Unitrode 
Logotipo Unitrode Logotipo



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Brushless DC Motor Controller
application
INFO
available
UC1625
UC2625
UC3625
FEATURES
Drives Power MOSFETs or Power Darlingtons
Directly
50V Open Collector High-Side Drivers
Latched Soft Start
High-speed Current-Sense Amplifier with Ideal
Diode
Pulse-by-Pulse and Average Current Sensing
Over-Voltage and Under-Voltage Protection
Direction Latch for Safe Direction Reversal
Tachometer
Trimmed Reference Sources 30mA
Programmable Cross-Conduction Protection
Two-Quadrant and Four-Quadrant Operation
DESCRIPTION
The UC3625 family of motor controller ICs integrate most of the
functions required for high-performance brushless DC motor con-
trol into one package. When coupled with external power
MOSFETs or Darlingtons, these ICs perform fixed-frequency PWM
motor control in either voltage or current mode while implementing
closed loop speed control and braking with smart noise rejection,
safe direction reversal, and cross–conduction protection.
Although specified for operation from power supplies between 10V
and 18V, the UC1625 can control higher voltage power devices
with external level-shifting components. The UC1625 contains fast,
high-current push-pull drivers for low-side power devices and 50V
open-collector outputs for high-side power devices or level shifting
circuitry.
The UC1625 is characterized for operation over the military tem-
perature range of –55°C to +125°C, while the UC2625 is charac-
terized from –40°C to +105°C and the UC3625 is characterized
from 0°C to 70°C. (NOTE: ESD Protection to 2kV)
TYPICAL APPLICATION
QUAD
DIR
VREF
+5V TO HALL
SENSORS
+15V
VMOTOR
100nF
20µF
10k
ROSC 3k10k
33k
2
22
100nF
6
1k
1
100nF 28
4k
27
UC3625
2200pF
COSC
25
15
BRAKE
21 26 3 24 23 8 9 10
+
20µF
19 11
16
17
18
14
13
12
20
457
3k
2N3904
10
2N3906
IRF9350
3k
TO OTHER
CHANNELS
TO OTHER
CHANNELS
10IRF532
10k
+
100µF
TO
MOTOR
REQUIRED
FOR BRAKE
AND FAST
REVERSE
3nF 68k
CT RT 5nF
100nF
2nF
2nF
2nF
FROM
HALL
SENSORS
5nF
100nF
240
240
0.02
RS
REQUIRED
FOR
AVERAGE
CURRENT
SENSING
0.02
RD
SLUS353A - NOVEMBER 1999
UDG-99045

1 page




UC3625 pdf
PIN DESCRIPTIONS
Dir, Speed-In: The position decoder logic translates the
Hall signals and the Dir signal to the correct driver sig-
nals (PUs and PDs). To prevent output stage damage,
the signal on Dir is first loaded into a direction latch,
then shifted through a two-bit register.
As long as Speed-In is less than 250mV, the direction
latch is transparent. When Speed-In is higher than
250mV, the direction latch inhibits all changes in direc-
tion. Speed-In can be connected to Tach-Out through a
filter, so that the direction latch is only transparent when
the motor is spinning slowly, and has too little stored en-
ergy to damage power devices.
Additional circuitry detects when the input and output of
the direction latch are different, or when the input and
output of the shift register are different, and inhibits all
output drives during that time. This can be used to allow
the motor to coast to a safe speed before reversing.
The shift register guarantees that direction can't be
changed instantaneously. The register is clocked by the
PWM oscillator, so the delay between direction changes
is always going to be between one and two oscillator pe-
riods. At 40kHz, this corresponds to a delay of between
25µs and 50µs. Regardless of output stage, 25µs dead
time should be adequate to guarantee no overlap
cross-conduction. Toggling DIR will cause an output
pulse on Tach-Out regardless of motor speed.
E/A In(+), E/A In(–), E/A Out, PWM In: E/A In(+) and
E/A In(–) are not internally committed to allow for a wide
variety of uses. They can be connected to the ISENSE, to
Tach-Out through a filter, to an external command volt-
age, to a D/A converter for computer control, or to an-
other op amp for more elegant feedback loops. The
error amplifier is compensated for unity gain stability, so
E/A Out can be tied to E/A In(–) for feedback and major
loop compensation.
E/A Out and PWM In drive the PWM comparator. For
voltage-mode PWM systems, PWM In can be connected
to RC-Osc. The PWM comparator clears the PWM latch,
commanding the outputs to chop.
The error amplifier can be biased off by connecting E/A
In(–) to a higher voltage than E/A In(+). When biased
off, E/A Out will appear to the application as a resistor to
ground. E/A Out can then be driven by an external am-
plifier.
GND: All thresholds and outputs are referred to the
GND pin except for the PD and PU outputs.
UC1625
UC2625
UC3625
H1, H2, H3: The three shaft-position sensor inputs con-
sist of hysteresis comparators with input pull-up resis-
tors. Logic thresholds meet TTL specifications and can
be driven by 5V CMOS, 12V CMOS, NMOS, or
open-collectors.
Connect these inputs to motor shaft position sensors
that are positioned 120 electrical degrees apart. If noisy
signals are expected, zener clamp and filter these inputs
with 6V zeners and an RC filter. Suggested filtering
components are 1kand 2nF. Edge skew in the filter is
not a problem, because sensors normally generate
modified Gray code with only one output changing at a
time, but rise and fall times must be shorter than 20µs
for correct tachometer operation.
Motors with 60 electrical degree position sensor coding
can be used if one or two of the position sensor signals
is inverted.
ISENSE1, ISENSE2, ISENSE: The current sense amplifier
has a fixed gain of approximately two. It also has a
built-in level shift of approximately 2.5V. The signal ap-
pearing on ISENSE is:
( )( )ISENSE = 2.5V + 2 ABS ISENSE1 ISENSE 2
ISENSE1 and ISENSE2 are interchangeable and can be
used as differential inputs. The differential signal applied
can be as high as ±0.5V before saturation.
If spikes are expected on ISENSE1 or ISENSE2, they are
best filtered by a capacitor from ISENSE to ground. Fil-
tering this way allows fast signal inversions to be cor-
rectly processed by the absolute value circuit. The
peak-current comparator allows the PWM to enter a cur-
rent-limit mode with current in the windings never ex-
ceeding approximately 0.2V/RSENSE. The over current
comparator provides a fail-safe shutdown in the unlikely
case of current exceeding 0.3V/RSENSE. Then, soft start
is commanded, and all outputs are turned off until the
high current condition is removed. It is often essential to
use some filter driving ISENSE1 and ISENSE2 to reject ex-
treme spikes and to control slew rate. Reasonable start-
ing values for filter components might be 250series
resistors and a 5nF capacitor between ISENSE1 and
ISENSE2. Input resistors should be kept small and
matched to maintain gain accuracy.
OV-Coast: This input can be used as an over-voltage
shutdown in put, as a coast input, or both. This input
can be driven by TTL, 5V CMOS, or 12V CMOS.
5

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UC3625 arduino
APPLICATION INFORMATION (cont.)
UC1625
UC2625
UC3625
Figure 8. Fast high-side P-channel driver.
Figure 11. Power NPN low-side driver.
Figure 9. Optocoupled N-channel high-side driver.
Figure 10. Power NPN high-side driver.
For drives where speed is critical, P-Channel MOSFETs
can be driven by emitter followers as shown in Fig. 8.
Here, both the level shift NPN and the PNP must with-
stand high voltages. A zener diode is used to limit
gate-source voltage on the MOSFET. A series gate re-
sistor is not necessary, but always advisable to control
overshoot and ringing.
High-voltage optocouplers can quickly drive high-voltage
MOSFETs if a boost supply of at least 10 volts greater
than the motor supply is provided (See Fig. 9.) To protect
the MOSFET, the boost supply should not be higher than
18 volts above the motor supply.
For under 200V 2-quadrent applications, a power NPN
driven by a small P-Channel MOSFET will perform well
as a high-side driver as in Fig. 10. A high voltage
small-signal NPN is used as a level shift and a high volt-
age low-current MOSFET provides drive. Although the
NPN will not saturate if used within its limitations, the
base-emitter resistor on the NPN is still the speed limiting
component.
Fig. 11 shows a power NPN Darlington drive technique
using a clamp to prevent deep saturation. By limiting sat-
uration of the power device, excessive base drive is mini-
mized and turn-off time is kept fairly short. Lack of base
series resistance also adds to the speed of this ap-
proach.
11

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