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PDF UPD4516161D Data sheet ( Hoja de datos )
| Número de pieza | UPD4516161D | |
| Descripción | 16M Bit Synchronous DRAM | |
| Fabricantes | Elpida | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4516161D
16M-bit Synchronous DRAM
2-banks, LVTTL
Description
The µPD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as
524,288 words × 16 bits × 2 banks respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
This product is packaged in 50-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Dual internal banks controlled by A11
• Byte control by LDQM and UDQM
• Programmable Wrap sequence: Sequential / Interleave
• Programmable burst length: 1, 2, 4, 8 and full page
• /CAS latency: 3
• CBR (Auto) refresh and self refresh
• ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 2,048 refresh cycles / 32 ms
• Burst termination by Burst stop command and Precharge command
Ordering Information
Part number
µPD4516161DG5-A70-9NF
µPD4516161DG5-A75-9NF
µPD4516161DG5-A80-9NF
µPD4516161DG5-A10-9NF
Organization
(word × bit × bank)
512K × 16 × 2
Clock frequency
MHz (MAX.)
143
133
125
100
Package
50-pin PLASTIC TSOP (II)
(10.16mm(400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0143N10 (Ver.1.0)
(Previous No. M14888EJ2V0DS00)
Date Published May 2001 CP (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
CONTENTS
µPD4516161D
1. Input / Output Pin Function............................................................................................................... 7
2. Commands.......................................................................................................................................... 8
3. Simplified State Diagram ................................................................................................................ 11
4. Truth Table ....................................................................................................................................... 12
4.1 Command Truth Table ............................................................................................................................. 12
4.2 DQM Truth Table ...................................................................................................................................... 12
4.3 CKE Truth Table ....................................................................................................................................... 12
4.4 Operative Command Table ..................................................................................................................... 13
4.5 Command Truth Table for CKE .............................................................................................................. 16
4.6 Command Truth Table for Two Banks Operation.................................................................................. 17
5. Initialization ..................................................................................................................................... 18
6. Programming the Mode Register .................................................................................................. 19
7. Mode Register ................................................................................................................................. 20
7.1 Burst Length and Sequence ................................................................................................................... 21
8. Address Bits of Bank-Select and Precharge ................................................................................ 22
9. Precharge ......................................................................................................................................... 23
10. Read / Write Command Interval .................................................................................................... 24
10.1 Read to Read Command Interval ........................................................................................................ 24
10.2 Write to Write Command Interval ........................................................................................................ 24
10.3 Write to Read Command Interval ........................................................................................................ 25
10.4 Read to Write Command Interval ........................................................................................................ 26
11. Burst Termination ........................................................................................................................... 27
11.1 Burst Stop Command ........................................................................................................................... 27
11.2 Precharge Termination ........................................................................................................................ 28
11.2.1 Precharge Termination in READ Cycle .................................................................................... 28
11.2.2 Precharge Termination in WRITE Cycle .................................................................................. 28
Data Sheet E0143N10
5
5 Page 
3. Simplified State Diagram
Mode
Register
Set
MRS
µPD4516161D
IDLE
SELF
SELF exit
REF
Self
Refresh
CBR (Auto)
Refresh
CKE
CKE
Power
Down
Write
BST
Write
ROW
ACTIVE
CKE
CKE
Read BST
Active
Power
Down
Read
WRITE
SUSPEND
CKE
CKE
WRITE
Read
Write
READ
CKE
CKE
READ
SUSPEND
POWER
ON
Precharge
Precharge
Data Sheet E0143N10
Automatic sequence
Manual input
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD4516161D.PDF ] | |
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