PDF IBM3206K0424 Data sheet ( Hoja de datos )

Número de pieza	IBM3206K0424
Descripción	IBM Processor for Network Resources
Fabricantes	IBM
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No Preview Available !  IBM Processor for Network Resources Revision 2.5 Databook Preliminary 1 page IBM3206K0424 Preliminary IBM Processor for Network Resources INTST CPB Capture Enable .......................................................................................................... 144 INTST CPB Captured Address ...................................................................................................... 145 INTST General Purpose Timer Pre-scaler .................................................................................... 145 INTST General Purpose Timer Compare ...................................................................................... 146 INTST General Purpose Timer Counter ........................................................................................ 146 INTST General Purpose Timer Status ........................................................................................... 147 INTST General Purpose Timer Mode Control ............................................................................... 148 INTST Enable for PCORE Normal Interrupt .................................................................................. 149 INTST Enable for PCORE Critical Interrupt ................................................................................... 149 INTST Debug States Control ......................................................................................................... 150 INTST Delayed Interrupts DMA System Address 1 ....................................................................... 152 INTST Delayed Interrupts DMA System Address 2 ....................................................................... 152 Current PCI Master Address Counter for Debug ........................................................................... 152 External Entity States Read ........................................................................................................... 153 DMA QUEUES (DMAQS) .................................................................................................................... 154 DMA Descriptors ........................................................................................................................... 154 DMA Types and Options ............................................................................................................... 155 Descriptor Based DMAs ................................................................................................................ 156 Register Based DMAs ................................................................................................................... 156 Polling, Interrupts, or Events ......................................................................................................... 156 Error Detection and Recovery ....................................................................................................... 156 DMA/Queue Scheduling Options ................................................................................................... 156 Address Size ................................................................................................................................. 156 Data Width ..................................................................................................................................... 157 Initialization of DMAQS .................................................................................................................. 157 DMAQS Lower Bound Registers ................................................................................................... 158 DMAQS Upper Bound Registers ................................................................................................... 159 DMAQS Head Pointer Registers ................................................................................................... 160 DMAQS Tail Pointer Registers ...................................................................................................... 160 DMAQS Length Registers ............................................................................................................. 161 DMAQS Threshold Registers ........................................................................................................ 161 DMAQS Interrupt Status ................................................................................................................ 162 DMAQS Interrupt Enable ............................................................................................................... 164 DMAQS Control Register .............................................................................................................. 164 DMAQS Enqueue DMA Descriptor Primitive ................................................................................. 166 DMAQS Source Address Register ................................................................................................ 166 DMAQS Destination Address Register .......................................................................................... 167 DMAQS Buffer Address Register .................................................................................................. 167 DMAQS Transfer Count and Flag Register ................................................................................... 168 DMAQS System Descriptor Address ............................................................................................. 171 DMAQS Checksum Register ......................................................................................................... 171 DMAQS Local Descriptor Range Registers ................................................................................... 173 DMAQS Event Queue Number Register ....................................................................................... 173 DMAQS DMA Request Size Register ............................................................................................ 174 DMAQS Enq FIFO Register .......................................................................................................... 174 General Purpose DMA (GPDMA) ...................................................................................................... 175 GPDMA Interrupt Status ................................................................................................................ 175 GPDMA Interrupt Enable ............................................................................................................... 176 GPDMA Control Register .............................................................................................................. 177 GPDMA Source Address Register ................................................................................................ 178 GPDMA Destination Address Register .......................................................................................... 179 nrm.toc.01 August 14, 2000 Page 5 5 Page Preliminary IBM3206K0424 IBM Processor for Network Resources RXQUE Dequeue Registers .......................................................................................................... 390 RXQUE Enqueue Registers .......................................................................................................... 391 RXQUE Next Lower Bound Registers ........................................................................................... 392 RXQUE Last Event Dropped Register ........................................................................................... 393 RXQUE Timestamp Register ......................................................................................................... 393 RXQUE Timestamp Pre-Scaler Register ....................................................................................... 393 RXQUE Timestamp Shift Register ................................................................................................ 394 RXQUE Event Routing Registers .................................................................................................. 394 RXQUE Event Latency Timer Register ......................................................................................... 395 RXQUE Queues Status Register ................................................................................................... 396 RXQUE Interrupt Enable Registers ............................................................................................... 397 RXQUE Status and Enabled Status Registers .............................................................................. 398 RXQUE Control Register ............................................................................................................... 400 Debugging Register Access .......................................................................................................... 401 RXQUE RXQ State Machine Variable Register ............................................................................ 401 RXQUE RXQ ENQ State Machine Variable Register .................................................................... 401 RXQUE Enq FIFO Head Ptr Register ............................................................................................ 402 RXQUE Enq FIFO Tail Ptr Register .............................................................................................. 402 RXQUE Enq FIFO Array ................................................................................................................ 402 PHY Level Interfaces ................................................................................................... 403 The PHY Interface (LINKC) ................................................................................................................ 403 Functional Description ................................................................................................................... 403 Multi-Drop ...................................................................................................................................... 403 POS-PHY ...................................................................................................................................... 403 Moving Cells To and From the IBM3206K0424 ............................................................................. 404 LINKC Global Control Register ...................................................................................................... 404 LINKC Configuration 0 Transmit & Receive Control Register ....................................................... 407 LINKC Configuration 1 Transmit & Receive Control Register ....................................................... 410 LINKC Configuration 2 Transmit & Receive Control Register ....................................................... 413 LINKC Configuration 3 Transmit & Receive Control Register ....................................................... 416 LINKC Map Transmit Configurations to Port Addresses ............................................................... 419 LINKC Map Receive Configurations to Port Addresses ................................................................ 420 LINKC Transmitted HEC Control Byte ........................................................................................... 421 LINKC Interrupt/Status Register .................................................................................................... 422 LINKC Interrupt Enable Register ................................................................................................... 424 LINKC Prioritized Interrupts ........................................................................................................... 424 LINKC Transmit State Machine Register ....................................................................................... 425 LINKC Receive State Machine Register ........................................................................................ 425 LINKC LAN Address Register ....................................................................................................... 426 LINKC Canonical LAN Address Register ...................................................................................... 426 LINKC Passed TX Data Register .................................................................................................. 427 Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data ........................................................................................................................ 428 NPBUS Control Register ............................................................................................................... 428 NPBUS Status Register ................................................................................................................. 431 NPBUS Interrupt Enable Register ................................................................................................. 432 NPBUS EPROM Address/Command Register .............................................................................. 433 NPBUS EPROM Data Register ..................................................................................................... 434 PHY 1 Registers ............................................................................................................................ 434 PHY 2 Registers ............................................................................................................................ 434 nrm.toc.01 August 14, 2000 Page 11 11 Page

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