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PDF TC58DVG02A1F00 Data sheet ( Hoja de datos )
| Número de pieza | TC58DVG02A1F00 | |
| Descripción | 1 Gbit (128M x *8its) CMOS NAND EPROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TC58DVG02A1FT00
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1-GBIT (128M × 8 BITS) CMOS NAND E2PROM
DESCRIPTION
The TC58DVG02A1 is a single 3.3 V 1-Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell
array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes:
528 bytes × 32 pages).
The TC58DVG02A1 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell allay 528 × 256K × 8
Register
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
• Modes
Read, Reset, Auto Page Program,
Auto Block Erase, Status Read,
Multi Block Program, Multi Block Erase
• Mode control
Serial input/output
Command control
• Power supply
VCC = 2.7 V to 3.6 V
• Program/Erase Cycles 1E5 cycle (with ECC)
• Access time
Cell array to register 25 µs max
Serial Read Cycle 50 ns min
• Operating current
Read (50 ns cycle) 10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
50 µA max.
• Package
TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
NC
NC
NC
NC
NC
GND
RY/BY
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 NC
47 NC
46 NC
45 NC
44 I/O8
43 I/O7
42 I/O6
41 I/O5
40 NC
39 NC
38 NC
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
I/O1 to I/O8
CE
WE
RE
CLE
ALE
WP
RY/BY
GND
VCC
VSS
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground input
Power supply
Ground
1 2003-11-11
1 page  
AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
TC58DVG02A1FT00
CONDITION
2.4 V, 0.4 V
3 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
CL (100 pF) + 1 TTL
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE
delay is less than 30 ns, RY/BY signal stays Ready.
tCEH ≥ 100 ns
* *: VIH or VIL
CE
RE
525 526 527 A
RY/BY
Busy
tCRY
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = 0° to 70°C, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
tPROG
tDBSY
Programming Time
Dummy Busy Time for Multi Block
Programming
tMBPBSY
N
Multi Block Program Busy Time
Number of Programming Cycles on Same
Page
2
tBERASE
Block Erasing Time
(1): Refer to Application Note (12) toward the end of this document.
TYP.
200
2
200
2
A : 0 to 30 ns → Busy signal is not
output.
MAX
1000
10
1000
3
10
UNIT
µs
µs
µs
ms
NOTES
(1)
5 2003-11-11
5 Page 
Sequential Read (1) Timing Diagram
CLE
TC58DVG02A1FT00
CE
WE
ALE
RE
I/O1
to 00h
RY/BY
A0 A9 A17 A25
to to to to
A7 A16 A24 A26
N N + 1 N + 2 527
012
Column
address
Page
address
tR
tR
NM
Page M
access
Page M + 1
access
: VIH or VIL
Sequential Read (2) Timing Diagram
CLE
527
CE
WE
ALE
RE
I/O1
to 01h
RY/BY
A0 A9 A17 A25
to to to to
A7 A16 A24 A26
Column
Page
address address
NM
tR
256 + 256 + 256 +
N N+1 N+2
527
tR
012
527
Page M
access
11
Page M + 1
access
: VIH or VIL
2003-11-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TC58DVG02A1F00.PDF ] | |
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