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PDF EPC1441xxx Data sheet ( Hoja de datos )

Número de pieza EPC1441xxx
Descripción Configuration Devices for SRAM-Based LUT Devices
Fabricantes Altera 
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February 2002, ver. 12.1
Configuration Devices for
® SRAM-Based LUT Devices
Data Sheet
Features
Serial device family for configuring APEXTM II, APEX 20K (including
APEX 20K, APEX 20KC, and APEX 20KE), MercuryTM, ACEX® 1K,
and FLEX® (FLEX 6000, FLEX 10KE, and FLEX 10KA) devices
Easy-to-use 4-pin interface to APEX II, APEX 20K, Mercury, ACEX,
and FLEX devices
Low current during configuration and near-zero standby current
5.0-V and 3.3-V operation
Software design support with the Altera® Quartus® II and
MAX+PLUS® II development systems for Windows-based PCs as
well as Sun SPARCstation, and HP 9000 Series 700/800
Programming support with Altera’s Master Programming Unit
(MPU) and programming hardware from Data I/O,
BP Microsystems, and other manufacturers
Available in compact plastic packages (see Figures 1 and 2)
– 8-pin plastic dual in-line package (PDIP)
– 20-pin plastic J-lead chip carrier (PLCC) package
– 32-pin plastic thin quad flat pack (TQFP) package
– 100-pin plastic thin quad flat pack (TQPF) package
– 88-pin Ultra FineLine BGATM package
EPC2 device has reprogrammable Flash configuration memory
– 5.0-V and 3.3-V in-system programmability (ISP) through the
built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG)
interface
– Built-in JTAG boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
– ISP circuitry is compatible with IEEE Std. 1532 for EPC2
configuration device
– Supports programming through Serial Vector Format Files
(.svf), JamTM Standard Test and Programming Language
(STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the
MAX+PLUS II software via the MasterBlasterTM,
ByteBlasterMVTM, or BitBlasterTM download cable
nINIT_CONF pin allows a JTAG instruction to initiate device
configuration
– Can be programmed with Programmer Object Files (.pof) for
EPC1 and EPC1441 devices
– Available in 20-pin PLCC and 32-pin TQFP packages
Altera Corporation
DS-EPROM-12.1
1

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EPC1441xxx pdf
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 2. Configuration Devices Used for Each APEX II, APEX 20K, Mercury, ACEX & FLEX Device
(Part 2 of 2)
Family
Device
Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16
(bits) EPC1064V
FLEX 10KE
(2.5 V)
FLEX 10KA
(3.3 V)
FLEX 10K
(5.0 V)
FLEX
6000/A
(3.3 V)
FLEX
8000A
(5.0 V)
EPF10K30E
EPF10K50E
EPF10K50S
EPF10K100B
EPF10K100E
EPF10K130E
EPF10K200E
EPF10K200S
EPF10K10A
EPF10K30A
EPF10K50V
EPF10K100A
EPF10K130V
EPF10K250A
EPF10K10
EPF10K20
EPF10K30
EPF10K40
EPF10K50
EPF10K70
EPF10K100
EPF6010A
EPF6016
(5.0 V) /
EPF6016A
EPF6024A
EPF8282A /
EPF8282AV
(3.3 V)
EPF8452A
EPF8636A
EPF8820A
EPF81188A
EPF1500A
470,000
785,000
785,000
1,2000,000
1,336,000
1,840,000
2,757,000
2,757,000
120,000
402,000
621,000
1,200,000
1,582,000
3,292,000
118,000
231,000
376,000
498,000
621,000
893,000
1,200,000
260,000
260,000
398,000
40,000
64,000
96,000
128,000
192,000
250,000
1
1
1111
1
1111
1
1111
1
111
1
111
1
211
1
211
1
211
1
1
1
1111
1
1
1111
1
1
1111
1
1111
1
1111
1
211
1
1
1
1111
1
1
1111
1
1
1111
1
1111
1
1111
1
1111
1
111
1
11
11
11
1 11
1 11
1 11
1 11
1 11
11
Altera Corporation
5

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EPC1441xxx arduino
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
& FLEX 6000 Configuration (Part 2 of 3) Notes (1), (2)
Pin Name
Pin Number
8-Pin 20-Pin 32-Pin
PDIP (3) PLCC TQFP (4)
Pin
Type
Description
nCASC (6) 6
nINIT_CONF
(5), (7)
TDI (7)
TDO (7)
TMS (7)
TCK (7)
VCCSEL (7)
VPPSEL (7)
VPP (7)
12 15 Output Cascade select output (active low). This output goes
low when the address counter has reached its
maximum value. In a chain of EPC1 or EPC2 devices,
the nCASC pin of one device is connected to the nCS pin
of the next device, which permits DCLK to clock data
from the next EPC1 or EPC2 device in the chain.
13 16 Open- Allows the INIT_CONF JTAG instruction to initiate
Drain configuration. This pin is connected to the nCONFIG pin
Output of the LUT device to initiate configuration from the
EPC2 via a JTAG instruction. If multiple EPC2 devices
are used to configure an ACEX, APEX, FLEX or
Mercury device, only the first EPC2 has its
nINIT_CONF pin tied to the device’s nCONFIG pin.
11 13 Input JTAG data input pin. Connect this pin to VCC if the
JTAG circuitry is not used.
1 28 Output JTAG data output pin. Do not connect this pin if the
JTAG circuitry is not used.
19 25 Input JTAG mode select pin. Connect this pin to VCC if the
JTAG circuitry is not used.
3 32 Input JTAG clock pin. Connect this pin to ground if the JTAG
circuitry is not used.
5 3 Input Mode select for VCC supply. VCCSEL must be
connected to ground if the device uses a 5.0-V power
supply (i.e., VCC = 5.0 V). VCCSEL must be connected
to VCC if the device uses a 3.3-V power supply (i.e.,
VCC = 3.3 V).
14 17 Input Mode select for VPP. VPPSEL must be connected to
ground if VPP uses a 5.0-V power supply
(i.e., VPP = 5.0 V). VPPSEL must be connected to VCC
if VPP uses a 3.3-V power supply (i.e, VPP = 3.3 V).
18 23 Power Programming power pin. For the EPC2 device, this pin
is normally tied to VCC. If the EPC2 VCC is 3.3 V, VPP
can be tied to 5.0 V to improve in-system programming
times. For EPC1 and EPC1441 devices, VPP must be
tied to VCC.
Altera Corporation
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