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PDF CA3160 Data sheet ( Hoja de datos )
| Número de pieza | CA3160 | |
| Descripción | 4MHz / BiMOS Operational Amplifier with MOSFET Input/CMOS Output | |
| Fabricantes | Intersil | |
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Data Sheet
CA3160, CA3160A
September 1998
File Number 976.3
4MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
The CA3160A and CA3160 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CA3160 series are
frequency compensated versions of the popular CA3130
series.
Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common-mode input voltage capability
down to 0.5V below the negative supply terminal, an
important attribute in single supply applications.
A complementary symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.
The CA3160 Series circuits operate at supply voltages
ranging from 5V to 16V, or ±2.5V to ±8V when using split
supplies, and have terminals for adjustment of offset voltage
for applications requiring offset null capability. Terminal
provisions are also made to permit strobing of the output
stage.
The CA3160A offers superior input characteristics over
those of the CA3160.
Ordering Information
PART NUMBER
CA3160AE
CA3160E
CA3160T
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 8 Ld PDIP
-55 to 125 8 Ld PDIP
-55 to 125 8 Pin Metal Can
PKG.
NO.
E8.3
E8.3
T8.C
Features
• MOSFET Input Stage Provides:
- Very High ZI = 1.5TΩ (1.5 x 1012Ω) (Typ)
- Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation
• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be Swung
0.5V Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
Both) Supply Rails
Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample Hold Amplifiers
• Long Duration Timers/Monostables
• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)
• Wien-Bridge Oscillators
• Voltage Controlled Oscillators
• Photo Diode Sensor Amplifiers
Pinouts
CA3160
(METAL CAN)
TOP VIEW
SUPPLEMENTARY
COMPENSATION
OFFSET 1
NULL
INV. 2
INPUT
TAB
8
-
+
STROBE
7 V+
6 OUTPUT
NON-INV. 3
INPUT
5 OFFSET
4 NULL
V- AND CASE
CA3160
(PDIP)
TOP VIEW
OFFSET NULL 1
INV.
INPUT
NON-INV.
INPUT
2
3
V- 4
-
+
8 STROBE
7 V+
6 OUTPUT
5 OFFSET NULL
NOTE: CA3160 Series devices have an on-chip frequency
compensation network. Supplementary phase compensation or
frequency roll-off (if desired) can be connected externally between
Terminals 1 and 8.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1 page  
CA3160, CA3160A
transistor Q11 and its cascode-connected load resistance
provided by PMOS transistors Q3 and Q5. The source of bias
potentials for these PMOS transistors is described later. Miller
Effect compensation (roll off) is accomplished by means of the
30pF capacitor and 2kΩ resistor connected between the base
and collector of transistor Q11. These internal components
provide sufficient compensation for unity gain operation in
most applications. However, additional compensation, if
desired, may be used between Terminals 1 and 8.
Bias-Source Circuit - At total supply voltages, somewhat
above 8.3V, resistor R2 and zener diode Z1 serve to establish a
voltage of 8.3V across the series-connected circuit, consisting
of resistor R1, diodes D1 through D4, and PMOS transistor Q1.
A tap at the junction of resistor R1 and diode D4 provides a
gate-bias potential of about 4.5V for PMOS transistors Q4 and
Q5 with respect to Terminal 7. A potential of about 2.2V is
developed across diode-connected PMOS transistor Q1 with
respect to Terminal 7 to provide gate bias for PMOS transistors
Q2 and Q3. It should be noted that Q1 is “mirror-connected” to
both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to
be identical, the approximately 200µA current in Q1 establishes
a similar current in Q2 and Q3 as constant-current sources for
both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z1 becomes nonconductive and the potential, developed
across series-connected R1, D1 - D4, and Q1, varies directly
with variations in supply voltage. Consequently, the gate bias
for Q4, Q5 and Q2, Q3 varies in accordance with supply-
voltage variations. This variation results in deterioration of the
power-supply-rejection ratio (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded performance.
Output Stage - The output stage consists of a drain-loaded
inverting amplifier using CMOS transistors operating in the
Class A mode. When operating into very high resistance loads,
the output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 17. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be encountered.
As a voltage follower, the amplifier can achieve 0.01% accuracy
levels, including the negative supply rail.
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer's total range.
Input Current Variation with Common Mode Input
Voltage
As shown in the Electrical Specifications, the input current for
the CA3160 Series Op Amps is typically 5pA at TA = 25oC
when Terminals 2 and 3 are at a common-mode potential of
+7.5V with respect to negative supply Terminal 4. Figure 23
contains data showing the variation of input current as a
function of common-mode input voltage at TA = 25oC. These
data show that circuit designers can advantageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common-mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate-protection diodes in the input circuit and,
therefore, a function of the applied voltage. Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate-
protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA3160 is also
internally tied to Terminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.
Input-Current Variation with Temperature
The input current of the CA3160 Series circuits is typically 5pA
at 25oC. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor junction device, including op
amps with a junction-FET input stage, the leakage current
approximately doubles for every 10oC increase in temperature.
Figure 24 provides data on the typical variation of input bias
current as a function of temperature in the CA3160.
In applications requiring the lowest practical input current and
incremental increases in current because of “warm-up” effects,
it is suggested that an appropriate heat sink be used with the
CA3160. In addition, when “sinking” or “sourcing” significant
output current the chip temperature increases, causing an
increase in the input current. In such cases, heat-sinking can
also very markedly reduce and stabilize input current variations.
Input Offset Voltage (VIO) Variation with DC Bias
vs Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magnitude
of the change is increased at high temperatures. Users of the
CA3160 should be alert to the possible impacts of this effect if
the application of the device involves extended operation at
high temperatures with a significant differential DC bias voltage
applied across Terminals 2 and 3. Figure 25 shows typical data
pertinent to shifts in offset voltage encountered with CA3160
devices in metal can packages during life testing. At lower
temperatures (metal can and plastic) for example at 85oC, this
change in voltage is considerably less. In typical linear
applications where the differential voltage is small and
symmetrical, these incremental changes are of about the same
5
5 Page 
CA3160, CA3160A
300V
100V
30V
10V
SW1A 3V
INPUT 1V
300V
100V
30V
10V
100MΩ
1.02
MΩ
300V
100V
30V
10V
9.9kΩ
BATTERY
TEST
OFF
ON
3 POSITION
SLIDE SWITCH
3V SW1B
1V 22MΩ
300V
100V
30V
10V
3
0.001µF
2
+9V
BATTERY
7
+
CA3160
-
5
1
4
6
300V
100V
30V
100kΩ
10V
SW1C 3V
ZERO
ADJUST 9.1kΩ
1V
300mV
10kΩ
100mV
30mV
BATTERY
3V CAL.
2.7kΩ 500Ω
820Ω 200Ω
1V CAL.
9kΩ
900Ω
300V
100V
30V
10V
3V
1V
300mV
100mV
30mV
10mV
+ 500
- µF
M
0-1mA
SW1D
10mV
100Ω
FIGURE 8. HIGH INPUT RESISTANCE DC VOLTMETER
20pF
8.2kΩ
+7.5V
VOLTAGE-CONTROLLED
CURRENT SOURCE
7
1kΩ
1kΩ
3
2
2MΩ
+
CA3080A
-
4
5
6
-7.5V
SYMMETRY 4.7kΩ
-7.5V 100kΩ +7.5V
0.9 - 7pF
C1
6.2kΩ
10-80pF
C2
BUFFER
VOLTAGE FOLLOWER
+7.5V
HIGH
FREQ.
SHAPE
7
3+
4 - 60pF CA3160
C3
2
-
EXTERNAL
SWEEPING INPUT
4
0.1µF
CENTERING
100kΩ
-7.5V
430pF
0.1µF
6.8MΩ
10kΩ
6
2
3
THRESHOLD
DETECTOR
+7.5V +7.5V
30kΩ
5
7
-
CA3080
6
+
-7.5V
10kΩ
MAX FREQ
SET
+7.5V
10kΩ 6.2kΩ
MIN FREQ.SET
500Ω
FREQ
500Ω
ADJUST
-7.5V
-7.5V
C4
4 - 60pF
2kΩ
HIGH FREQ
LEVEL
ADJUST
50kΩ
2-1N914
C5
15 - 115pF
FIGURE 9A. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CA3160.PDF ] | |
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