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PDF DS1236 Data sheet ( Hoja de datos )

Número de pieza DS1236
Descripción MicroManager Chip
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DS1236
MicroManager Chip
FEATURES
Holds microprocessor in check during power
transients
Halts and restarts an out-of-control
microprocessor
Monitors pushbutton for external override
Warns microprocessor of an impending power
failure
Converts CMOS SRAM into nonvolatile
memory
Unconditionally write-protects memory when
power supply is out of tolerance
Consumes less than 100 nA of battery current
at 25°C
Controls external power switch for high
current applications
Accurate 10% power supply monitoring
Optional 5% power supply monitoring
designated DS1236-5
Provides orderly shutdown in nonvolatile
microprocessor applications
Supplies necessary control for low-power
“stop mode” in battery operated hand-held
applications
Standard 16-pin DIP or space-saving 16-pin
SOIC
Optional industrial temperature range -40°C
to +85°C
PIN ASSIGNMENT
VBAT 1 16 RST
VCCO 2 15 RST
VCC
GND
PF
PF
WC/SC
RC
3
4
5
6
7
8
14 PBRST
13 CEI
VBAT
VCCO
12 CEO
VCC
11 ST
10 NMI
GND
PF
PF
9 IN
WC/SC
RCI
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
RST
RST
PBRST
CEI
CEO
ST
NMI
IN
16-Pin DIP (300-mil)
See Mech. Drawings Section
16-Pin SOIC (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
VBAT
VCCO
VCC
GND
- +3-Volt Battery Input
- Switched SRAM Supply Output
- +5-Volt Power Supply Input
- Ground
PF - Power-Fail (Active High)
PF - Power-Fail (Active Low)
WC/ SC
- Wake-Up Control (Sleep)
RC - Reset Control
IN - Early Warning Input
NMI - Non-Maskable Interrupt
ST - Strobe Input
CEO - Chip Enable Output
CEI - Chip Enable Input
PBRST
- Pushbutton Reset Input
RST - Reset Output (Active Low)
RST - Reset Output (Active High)
DESCRIPTION
The DS1236 MicroManager Chip provides all the necessary functions for power supply monitoring, reset
control, and memory backup in microprocessor-based systems. A precise internal voltage reference and
comparator circuit monitor power supply status. When an out-of-tolerance condition occurs, the
microprocessor reset and power-fail outputs are forced active, and static RAM control unconditionally
write protects external memory. The DS1236 also provides early warning detection of a user-defined
threshold by driving a non-maskable interrupt. External reset control is provided by a pushbutton reset
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DS1236 pdf
DS1236 FUNCTIONAL BLOCK DIAGRAM Figure 1
DS1236
If the IN pin is connected to VCCO, the NMI output will pulse low as VCC decays to VCCTP in the NMOS
mode (RC=0). In the CMOS mode (RC=VCCO) the power-down of VCC out-of-tolerance at VCCTP will not
produce a pulse on the NMI pin. Given that any NMI pulse has been completed by the time VCC decays
to VCCTP, the NMI pin will remain high. The NMI voltage will follow VCC down until VCC decays to
VBAT. Once VCC decays to VBAT, the NMI pin will either remain at VOHL or enter tri-state mode as
determined by the RC pin (see “Reset Control” section).
MEMORY BACKUP
The DS1236 provides all of the necessary functions required to battery back a static RAM. First, a switch
is provided to direct SRAM power from the incoming 5-volt supply (VCC) or from an external battery
(VBAT), whichever is greater. This switched supply (VCCO) can also be used to battery back a CMOS
microprocessor. For more information about nonvolatile processor applications, review the “Reset
Control” and “Wake Control” sections. Second, the same power-fail detection described in the power
monitor section is used to hold the chip enable output ( CEO ) to within 0.3 volts of VCC or to within 0.7
volts of VBAT. This write protection mechanism occurs as VCC falls below VCCTP as specified. If CEI is
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DS1236 arduino
DS1236
power-down in a sleep mode. Removal of the sleep mode by the PBRST input is not affected by the IN
pin threshold at VTP when the RC pin is tied high (CMOS mode). Subsequent power-up of the VCC supply
with the RC pin tied high will activate the RST and RST outputs as the main supply rises above VBAT. A
high-to-low transition on the WC/ SC pin must follow a high-to-low transition on the ST pin by tWC to
invoke a Sleep mode for the DS1236.
FRESHNESS SEAL Figure 8
NOTE: This series of pulses must be applied during normal +5 volt operation.
POWER SWITCHING Figure 9
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