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PDF FT2232L Data sheet ( Hoja de datos )
| Número de pieza | FT2232L | |
| Descripción | Dual USB UART / FIFO I.C | |
| Fabricantes | FTDI | |
| Logotipo |  |
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FT2232L Dual USB UART / FIFO I.C.
1.0 Introduction
The FT2232L is the lead free version of FTDI’s 3rd generation USB UART / FIFO I.C. family. This device features two
Multi-Purpose UART / FIFO controllers which can be configured individually in several different modes. As well as a
UART interface, FIFO interface and Bit-Bang IO modes of the 2nd generation FT232BM and FT245BM devices, the
FT2232L offers a variety of additional new modes of operation, including a Multi-Protocol Synchronous Serial Engine
interface which is designed specifically for synchronous serial protocols such as JTAG and SPI bus.
1.1 Features Summary
HARDWARE FEATURES
Reset input and Reset Output pins
• Single Chip USB Dual Channel Serial / Parallel • 5V and 3.3V logic IO Interfacing with independent
Ports with a variety of configurations
level conversion on each channel
• Entire USB protocol handled on the chip...no USB- • Integrated 3.3V LDO Regulator for USB IO
specific firmware programming required
• Integrated 6MHz – 48Mhz clock multiplier PLL
• FT232BM-style UART interface option with full
• USB Bulk or Isochronous data transfer modes
Handshaking & Modem interface signals
• 4.35V to 5.25V single supply operating voltage
• UART Interface supports 7 / 8 bit data, 1 / 2 stop
range
bits, and Odd / Even / Mark / Space / No Parity
• UHCI / OHCI / EHCI host controller compatible
• Transfer Data Rate 300 to 1 Mega Baud (RS232) • USB 2.0 Full Speed (12 Mbits / Second)
• Transfer Data Rate 300 to 3 Mega Baud (TTL and
compatible
RS422 / RS485)
• Compact 48-LD Lead Free LQFP package
• Auto Transmit Enable control for RS485 serial
VIRTUAL COM PORT (VCP) DRIVERS for
applications using TXDEN pin
• Windows 98 / 98 SE / 2000 / ME / XP
• FT245BM-style FIFO interface option with bi-
• Linux 2.40 and greater
directional data bus and simple 4 wire handshake • Windows CE
interface
• MAC OS-8 and OS-9**
• Transfer Data Rate up to 1 MegaByte / Second
• MAC OS-X
• Enhanced Bit-Bang Mode interface option
D2XX (USB Direct Drivers + DLL S/W Interface)
• New Synchronous Bit-Bang Mode interface option • Windows 98 / 98 SE / 2000 / ME / XP
• New Multi-Protocol Synchronous Serial Engine
• Linux 2.4 and Greater
(MPSSE) interface option
• New MCU Host Bus Emulation Mode option
• New Fast Opto-Isolated Serial Interface Mode
APPLICATION AREAS
• USB Dual Port RS232 Converters
• USB Dual Port RS422 / RS485 Converters
option
• Upgrading Legacy Peripheral Designs to USB
• Interface mode and USB Description strings
• USB Instrumentation
configurable in external EEPROM
• USB JTAG Programming
• EEPROM Configurable on board via USB
• USB to SPI Bus Interfaces
• Support for USB Suspend and Resume conditions • USB Industrial Control
via PWREN#, and SI / WU pins
• Field Upgradable USB Products
• Support for bus powered, self powered, and high- • Galvanically Isolated Products with USB Interface
power bus powered USB configurations
• Integrated Power-On-Reset circuit, with optional
[ ** = In planning or under development ]
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 1 of 54
1 page  
FT2232L Dual USB UART / FIFO I.C.
In addition to the BM chip features, the FT2232L incorporates the following new features and interface modes :-
• Enhanced Asynchronous Bit-Bang Interface
normally be un-configured (i.e. have no defined
The FT2232L supports FTDI’s BM chip Bit Bang
function) at power-up. Application software on the PC
mode. In Bit Bang mode, the eight FIFO data lines
could use the MPSSE to download configuration data
can be switched between FIFO interface mode
to the FPGA over USB. This data would define the
and an 8-bit Parallel IO port. Data packets can be
hardware’s function on power up. The other FT2232
sent to the device and they will be sequentially sent
channel would be available for other devices.
to the interface at a rate controlled by an internal
This approach would allow a customer to create a
timer (equivalent to the baud rate prescaler). With
“generic” USB peripheral, who’s hardware function
the FT2232L device this mode has been enhanced
can be defined under control of the application
so that the internal RD# and WR# strobes are now
software. The FPGA based hardware could be easily
brought out of the device which can be used to allow
external logic to be clocked by accesses to the Bit-
Bang IO bus.
upgraded or totally changed simply by changing the
FPGA configuration data file. (See FTDI’s MORPH-
IC development module for a practicle example,
• Synchronous Bit-Bang Interface
www.morph-ic.com)
Synchronous Bit-Bang Mode differs from
Asynchronous Bit-Bang mode in that the device
is only read when it is written to. Thus making it
easier for the controlling program to measure the
response to an output stimulus as the data returned
is synchronous to the output data.
• MCU Host Bus Emulation
This new mode combines the ‘A’ and ‘B’ bus interface
to make the FT2232L interface emulate a standard
8048 / 8051 style MCU bus. This allows peripheral
devices for these MCU families to be directly
attached to the FT2232L with IO being performed
• High Output Drive Level Capabillity
The IO interface pins can be made to drive out at
over USB with the help of MPSSE interface
technology.
three times the standard drive level thus allowing
multiple devices, or devices that require a greater
drive strength to be interfaced to the FT2232L. This
option is configured in the external EEPROM, ad can
be set individually for each channel.
• Fast Opto-Isolated Serial Interface
A new proprietary FTDI protocol is designed to
allow galvanically isolated devices to communicate
sychronously with the FT2232L using just 4 signal
wires (over two dual opto-isolators), and two power
• Multi-Protocol Synchronous Serial Engine
Interface (M.P.S.S.E.)
The Multi-Protocol Synchronous Serial Engine
(MPSSE) interface is a new option designed to
interface efficiently with synchronous serial protocols
such as JTAG and SPI Bus. It is very flexible in that it
lines. The peripheral circuitry controls the data
transfer rate in both directions, whilst maintaining
full data integrity. Maximum USB full speed data
rates can be acheived. Both ‘A’ and ‘B’ channels
can communicate over the same 4 wire interface if
desired.
can be configured for different industry standards, or
proprietary bus protocols. For instance, it is possible
to connect one of the FT2232L’s channels to an
SRAM configurable FPGA as supplied by vendors
such as Altera and Xilinx. The FPGA device would
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 5 of 54
5 Page 
FT2232L Dual USB UART / FIFO I.C.
POWER AND GND GROUP
Pin#
Signal
Type
Description
6 3V3OUT OUTPUT 3.3 volt Output from the integrated L.D.O. regulator This pin should be
decoupled to GND using a 33nF ceramic capacitor in close proximity to the
device pin. It’s prime purpose is to provide the internal 3.3V supply to the
USB transceiver cell and the RSTOUT# pin. A small amount of current (<=
5mA) can be drawn from this pin to power external 3.3V logic if required.
3, 42
VCC
PWR
+4.35 volt to +5.25 volt VCC to the device core, LDO and non-UART / FIFO
controller interface pins.
14
VCCIOA
PWR
+3.0 volt to +5.25 volt VCC to the UART / FIFO A Channel interface pins
10..13, 15..17 and 19..24. When interfacing with 3.3V external logic in a bus
powered design connect VCCIO to a 3.3V supply generated from the USB
bus. When interfacing with 3.3V external logic in a self powered design
connect VCCIO to the 3.3V supply of the external logic. Otherwise connect
to VCC to drive out at 5V CMOS level.
31
VCCIOB
PWR
+3.0 volt to +5.25 volt VCC to the UART / FIFO B Channel interface pins
26..30, 32..33 and 35..40. When interfacing with 3.3V external logic in a bus
powered design connect VCCIO to a 3.3V supply generated from the USB
bus. When interfacing with 3.3V external logic in a self powered design
connect VCCIO to the 3.3V supply of the external logic. Otherwise connect
to VCC to drive out at 5V CMOS level.
9,18, 25, 34 GND
PWR
Device - Ground Supply Pins
46
AVCC
PWR
Device - Analog Power Supply for the internal x8 clock multiplier. A low pass
filter consisting of a 470 Ohm series resistor and a 100 nF to GND should be
used on the supply to this pin.
45
AGND
PWR
Device - Analog Ground Supply for the internal x8 clock multiplier
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 11 of 54
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FT2232L.PDF ] | |
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