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PDF 80486GX Data sheet ( Hoja de datos )

Número de pieza 80486GX
Descripción Embedded Ultra-Low Power Processor
Fabricantes Intel 
Logotipo Intel Logotipo



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EMBEDDED ULTRA-LOW POWER Intel486GX PROCESSOR
s Ultra-Low Power Member of the Intel486™ s 16-Bit External Data Bus
Processor Family
— 32-Bit RISC Technology Core
— 8-Kbyte Write-Through Cache
— Four Internal Write Buffers
s 176-Lead Thin Quad Flat Pack (TQFP)
s Separate Voltage Supply for Core Circuitry
s Fast Core-Clock Restart
— Burst Bus Cycles
s Auto Clock Freeze
— Data Bus Parity Generation and
Checking
s Ideal for Embedded Battery-Operated and
Hand-Held Applications
— Intel System Management Mode (SMM)
— Boundary Scan (JTAG)
Barrel
Shifter
Register
File
ALU
Base/
Index
Bus
32
64-Bit Interunit Transfer Bus
32-Bit Data Bus
32
32-Bit Data Bus
32
Linear Address
32
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
Paging
Unit
PCD
PWT
2
20
Translation
Lookaside
Buffer
Physical
Address
Cache Unit
8 Kbyte
Cache
Core
Clock
Clock
Control
CLK Input
Bus Interface
32 Address
Drivers
Write Buffers
32 4 x 32
Data Bus
32 Transceivers
A31-A2
BE3#- BE0#
D15-D0
Micro-
Instruction
Displacement Bus
32
128
Prefetcher
Control &
Protection
Test Unit
Instruction
Decode
Code
Stream
24
32-Byte Code
Queue
2x16 Bytes
Control
ROM
Decoded
Instruction
Path
Bus Control
Request
Sequencer
Burst Bus
Control
ADS# W/R# D/C# M/IO#
PCD PWT RDY# LOCK#
PLOCK# BOFF# A20M#
BREQ HOLD HLDA
RESET SRESET INTR
NMI SMI# SMIACT#
STPCLK#
BRDY# BLAST#
Parity
Generation
and Control
Cache
Control
Boundary
Scan
Control
DP1-DP0, PCHK#
KEN# FLUSH#
AHOLD EADS#
TCK TMS
TDI TD0
A5851-01
Figure 1. Embedded Ultra-Low Power Intel486™ GX Processor Block Diagram
© INTEL CORPORATION, 1997
December 1997
Order Number: 272755-002

1 page




80486GX pdf
Embedded Ultra-Low Power Intel486™ GX Processor
1.0 INTRODUCTION
This data sheet describes the embedded Ultra-Low
Power (ULP) Intel486™ GX processor. It is intended
for embedded battery-operated and hand-held appli-
cations. The embedded ULP Intel486 GX processor
provides all of the features of the Intel486 SX
processor except for the 8-bit bus sizing logic and
the processor-upgrade pin. The processor typically
uses 20% to 50% less power than the Intel486 SX
processor. Additionally, the embedded ULP Intel486
GX processor external data bus and parity signals
have level-keeper circuitry and a fast-recovery core
clock which are vital for ultra-low-power system
designs. The processor is available in a Thin Quad
Flat Package (TQFP) enabling low-profile
component implementation.
The embedded ULP Intel486 GX processor consists
of a 32-bit integer processing unit, an on-chip cache,
and a memory management unit. The design
ensures full instruction-set compatibility with the
8086, 8088, 80186, 80286, Intel386™ SX, Intel386
DX, and all versions of Intel486 processors.
1.1 Features
The embedded ULP Intel486 GX processor offers
these features of the Intel486 SX processor:
32-bit RISC-Technology Core — The embedded
ULP Intel486 GX processor performs a complete
set of arithmetic and logical operations on 8-, 16-,
and 32-bit data types using a full-width ALU and
eight general purpose registers.
Single Cycle Execution — Many instructions
execute in a single clock cycle.
Instruction Pipelining — Overlapped instruction
fetching, decoding, address translation and
execution.
On-Chip Cache with Cache Consistency
Support — An 8-Kbyte, write-through, internal
cache is used for both data and instructions.
Cache hits provide zero wait-state access times
for data within the cache. Bus activity is tracked to
detect alterations in the memory represented by
the internal cache. The internal cache can be
invalidated or flushed so that an external cache
controller can maintain cache consistency.
External Cache Control — Write-back and flush
controls for an external cache are provided so the
processor can maintain cache consistency.
On-Chip Memory Management Unit — Address
management and memory space protection
mechanisms maintain the integrity of memory in a
multitasking and virtual memory environment. Both
segmentation and paging are supported.
Burst Cycles — Burst transfers allow a new 16-bit
data word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache. Burst transfers also occur on some
memory write and some I/O data transfers.
Write Buffers — The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.
Bus Backoff — When another bus master needs
control of the bus during a processor initiated bus
cycle, the embedded ULP Intel486 GX processor
floats its bus signals, then restarts the cycle when
the bus becomes available again.
Instruction Restart — Programs can continue
execution following an exception generated by an
unsuccessful attempt to access memory. This
feature is important for supporting demand-paged
virtual memory applications.
Boundary Scan (JTAG) — Boundary Scan
provides in-circuit testing of components on
printed circuit boards. The Intel Boundary Scan
implementation conforms with the IEEE Standard
Test Access Port and Boundary Scan Architecture.
1

5 Page





80486GX arduino
Embedded Ultra-Low Power Intel486™ GX Processor
3.2 Pin Quick Reference
The following is a brief pin description. For detailed signal descriptions refer to Appendix A, “Signal Descrip-
tions,” in the Embedded Intel486™ Processor Family Developer’s Manual, order No. 273021.
Table 4. Embedded ULP Intel486GX Processor Pin Descriptions (Sheet 1 of 6)
Symbol
CLK
Type
I
ADDRESS BUS
A31-A4
I/O
A3–A2
O
BE3#
BE2#
BE1#
BE0#
O
O
O
O
DATA BUS
D15–D0
I/O
DP1 I/O
DP0
Name and Function
Clock provides the fundamental timing and internal operating frequency for the
embedded ULP Intel486 GX processor. All external timing parameters are
specified with respect to the rising edge of CLK.
Address Lines A31–A2, together with the byte enable signals, BE3#–BE0#,
define the physical area of memory or input/output space accessed. Address lines
A31–A4 are used to drive addresses into the embedded ULP Intel486 GX
processor to perform cache line invalidation. Input signals must meet setup and
hold times t22 and t23. A31–A2 are not driven during bus or address hold.
Byte Enable signals indicate active bytes during read and write cycles. During the
first cycle of a cache fill, the external system should assume that all byte enables
are active. BE3#–BE0# are active LOW and are not driven during bus hold.
BE3# applies to processor data bits D31–D24
BE2# applies to processor data bits D23–D16
BE1# applies to processor data bits D15–D8
BE0# applies to processor data bits D7–D0
The byte enables can be used by the external system to generate address bits A1
and A0, as well as byte-high (D15-D8) and byte-low (D7-D0) enables. These are
needed to interpret the 16-bit external data bus.
Data Lines. D7–D0 define the least significant byte of the data bus; D15-D8 define
the most significant byte of the data bus. These signals must meet setup and hold
times t22 and t23 for proper operation on reads. These pins are driven during the
second and subsequent clocks of write cycles.
There is one Data Parity pin for each byte of the data bus. Data parity is generated
on all write data cycles with the same timing as the data driven by the embedded
ULP Intel486 GX processor. Even parity information must be driven back into the
processor on the data parity pins with the same timing as read information to
ensure that the correct parity check status is indicated by the processor. The
signals read on these pins do not affect program execution.
Input signals must meet setup and hold times t22 and t23. DP1 and DP0 must be
connected to VCCP through a pull-up resistor in systems that do not use parity. DP1
and DP0 are active HIGH and are driven during the second and subsequent clocks
of write cycles.
7

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