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Número de pieza | 80321 | |
Descripción | I/O Processor | |
Fabricantes | Intel | |
Logotipo | ||
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No Preview Available ! Intel® 80321 I/O Processor
Datasheet
Product Features
s Core Features
s DMA Controller
— Integrated Intel® XScale™ Core
— Two Independent Channels Connected
— ARM* V5T Instruction Set
— ARM V5E DSP Extensions
— 400 MHz and 600 MHz
— Write Buffer, Write-back Cache
to Internal Bus
— Up to 1064 MB/s Burst Support in
PCI-X Mode
— Up to 1600 MB/s Burst Support for
Internal Bus
s PCI Bus Interface
— Two 1-KB Queues in Ch-0 and Ch-1
— PCI Local Bus Specification, Rev. 2.2
compliant
— 232 Addressing Range on Internal Bus
Interface
— PCI-X Addendum to the PCI Local Bus
— 264 Addressing Range on PCI Interface
Specification, Rev. 1.0a
s Application Accelerator Unit
— 64-bit/66MHz Operation in PCI Mode
— Performs XOR on Read Data
—64-bit/133MHz Operation in PCI-X Mode — Compute Parity Across Local Memory
— Support 32-bit PCI Initiators and Targets
Blocks
— Four Split Read Requests as Initiator
— Eight Split Read Requests as Target
— 64-bit Addressing Support
— 1 KB/512-byte Store Queue
s I2C Bus Interface Units
— Two Separate I2C Units
s Memory Controller
— Serial Bus
—PC200 Double Data Rate (DDR) SDRAM — Master/Slave Capabilities
— Up to 1 GB of 64-bit DDR SDRAM
— System Management Functions
— Up to 512 MB of 32-bit DDR SDRAM s SSP Serial Port
— Single-bit Error Correction, Multi-bit
Support (ECC)
— Full-duplex Synchronous Serial Interface
— Supports 7.2 KHz to 1.84 MHz Bit Rates
— 1024-byte Posted Memory Write Queue s Peripheral Performance Monitoring Unit
— 40- and 72-bit wide Memory Interface
— One Dedicated Global Time Stamp
Counter
s Address Translation Unit
— Fourteen Programmable Event Counters
— 2 KB or 4 KB Outbound Read Queue
— Three Control/Status Registers
— 4 KB Outbound Write Queue
s Timers
— 4 KB Inbound Read and Write Queue
— Two Dual-programmable 32-bit Timers
—Connects Internal Bus to PCI/PCI-X Bus — Watchdog Timer
s 544-Ball, Plastic Ball Grid Array (PBGA)
s Eight General Purpose I/O Pins
Document Number: 273518-002
June 2002
1 page Intel® 80321 I/O Processor
Revision History
Date
Revision #
Description
June 2002
002 Removed Advance Information designation.
February 2002 001 Initial release.
Datasheet
June 2002
5
5 Page 2.0
2.1
2.2
Intel® 80321 I/O Processor
Features
Features
The 80321 combines the Intel® XScale™ core with powerful new features to create an intelligent
I/O processor. This single-function PCI device is fully compliant with the PCI Local Bus
Specification, Revision 2.2. 80321-specific features include:
• Address Translation Unit
• Memory Controller
• Peripheral Bus Interface
• Application Accelerator Unit
• DMA Controller
• Performance Monitoring Unit
• Synchronous Serial Port Unit
• Messaging Unit
• I2C Bus Interface Units
• I2O* Compatibility
The subsections that follow briefly overview each feature. Refer to the appropriate chapter in the
Intel® 80321 I/O Processor Developer’s Manual for full technical descriptions.
The 80321 core is based upon the Intel® XScale™ core. The core processor operates at a maximum
frequency of 600 MHz. The instruction cache is 32 Kbytes in size and is 32-way set associative.
Also, the core processor includes a data cache that is 32 Kbytes and is 32-way set associative and a
mini data cache that is 2 Kbytes and is 2-way set associative.
The 80321 includes 8 General Purpose I/O (GPIO) pins.
Internal Bus
The Internal Bus is a high-speed interconnect between all internal units and controllers. The
Internal Bus operates at 200 MHz and is 64 bits wide.
DMA Controller
The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents
and the local memory. Two separate DMA channels accommodate data transfers on the PCI bus.
The DMA Controller supports chaining and unaligned data transfers. It is programmable through
the Intel® XScale™ core only.
Datasheet
June 2002
11
11 Page |
Páginas | Total 30 Páginas | |
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