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PDF XC3S1500 Data sheet ( Hoja de datos )
| Número de pieza | XC3S1500 | |
| Descripción | Spartan-3 FPGa Family | |
| Fabricantes | Xilinx | |
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0
R Spartan-3 FPGA Family:
Complete Data Sheet
DS099 January 17, 2005
00
This document includes all four modules of the Spartan™-3 FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS099-1 (v1.4) January 17, 2005
6 pages
• Introduction
• Features
• Architectural Overview
• Product Availability
• User I/O Chart
• Ordering Information
Module 2:
Functional Description
DS099-2 (v1.3) August 24, 2004
40 pages
• IOBs
- IOB Overview
- SelectIO™ Signal Standards
• CLB Overview
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
- Clock Network
• Configuration
Module 3:
DC and Switching Characteristics
DS099-3 (v1.5) December 17, 2004
39 pages
• DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
• Switching Characteristics
- I/O Timing
- Internal Logic Timing
- DCM Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS099-4 (v1.6) January 17, 2005
112 pages
• Pin Descriptions
- Pin Behavior During Configuration
• Package Overview
• Pinout Tables
- Footprints
IMPORTANT NOTE: The Spartan-3 FPGA data sheet is created and published in separate modules. This complete version
is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for
each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in
this volume.
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099 January 17, 2005
www.xilinx.com
www.DataSheet4U.com
1 page  
Spartan-3 FPGA Family: Introduction and Ordering Information
R
Table 3: Spartan-3 I/O Chart
Available User I/Os and Differential (Diff) I/O Pairs
VQ100
VQG100
CP132
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG456
FGG456
FG676
FGG676
FG900
FGG900
FG1156
FGG1156
Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff
XC3S50 63 29 89 44 97 46 124 56 - - - - - - - - - - - -
XC3S200 63 29 - - 97 46 141 62 173 76 - - - - - - - - - -
XC3S400 - - - - 97 46 141 62 173 76 221 100 264 116 - - - - - -
XC3S1000 - - - - - - - - 173 76 221 100 333 149 391 175 - - - -
XC3S1500 - - - - - - - - - - 221 100 333 149 487 221 - - - -
XC3S2000 - - - - - - - - - - - - 333 149 489 221 565 270 - -
XC3S4000 - - - - - - - - - - - - - - 489 221 633 300 712 312
XC3S5000 - - - - - - - - - - - - - - - - 633 300 784 344
Notes:
1. All device options listed in a given package column are pin-compatible.
2. User = User I/O pins. Diff = Differential I/O pairs.
Package Marking
Device Type
Package
Speed Grade
Temperature Range
R
SPARTAN R
XC3S50TM
PQ208AFQ0350
xxxxxxxxx
4C
Mask Revision Code
Fabrication Code
F = UMC 8D (200 mm)
G = UMC 12A (300 mm)
Process Technology
Q = 90 nm
Date Code
Lot Code
ds099-1_03_011705
4
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DS099-1 (v1.4) January 17, 2005
Preliminary Product Specification
6
5 Page 
Spartan-3 FPGA Family: Functional Description
R
DCM
180˚ 0˚
D1
Q1
CLK1
D2
Q2
CLK2
FDDR
DDR MUX
Q
DS099-2_02_070303
Figure 2: Clocking the DDR Register
Pull-Up and Pull-Down Resistors
The optional pull-up and pull-down resistors are intended to
establish High and Low levels, respectively, at unused I/Os.
The pull-up resistor optionally connects each IOB pad to
VCCO. A pull-down resistor optionally connects each pad to
GND. These resistors are placed in a design using the
PULLUP and PULLDOWN symbols in a schematic, respec-
tively. They can also be instantiated as components, set as
constraints or passed as attributes in HDL code. These
resistors can also be selected for all unused I/O using the
Bitstream Generator (BitGen) option UnusedPin. A Low
logic level on HSWAP_EN activates the pull-up resistors on
all I/Os during configuration.
Keeper Circuit
Each I/O has an optional keeper circuit that retains the last
logic level on a line after all drivers have been turned off.
This is useful to keep bus lines from floating when all con-
nected drivers are in a high-impedance state. This function
is placed in a design using the KEEPER symbol. Pull-up
and pull-down resistors override the keeper circuit.
ESD Protection
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: One diode
extends P-to-N from the pad to VCCO and a second diode
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes lim-
its the ability of Spartan-3 I/Os to tolerate high signal volt-
ages. The VIN absolute maximum rating in Table 1 in
Module 3: DC and Switching Characteristics specifies the
voltage range that I/Os can tolerate.
Slew Rate Control and Drive Strength
Two options, FAST and SLOW, control the output slew rate.
The FAST option supports output switching at a high rate.
The SLOW option reduces bus transients. These options are
only available when using one of the LVCMOS or LVTTL
standards, which also provide up to seven different levels of
current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. Choos-
ing the appropriate drive strength level is yet another means
to minimize bus transients.
Table 3 shows the drive strengths that the LVCMOS and
LVTTL standards support. The Fast option is indicated by
appending an "F" attribute after the output buffer symbol
OBUF or the bidirectional buffer symbol IOBUF. The Slow
option appends an "S" attribute. The drive strength in milliam-
peres follows the slew rate attribute. For example,
OBUF_LVCMOS18_S_6 or IOBUF_LVCMOS25_F_16.
Table 3: Programmable Output Drive Current
Signal
Standard
Current Drive (mA)
2 4 6 8 12 16
LVCMOS12 3 3 3 - - -
LVCMOS15 3 3 3 3 3 -
LVCMOS18 3 3 3 3 3 3
LVCMOS25 3 3 3 3 3 3
LVCMOS33 3 3 3 3 3 3
LVTTL
333333
24
-
-
-
3
3
3
Boundary-Scan Capability
All Spartan-3 IOBs support boundary-scan testing compat-
ible with IEEE 1149.1 standards. See Boundary-Scan
(JTAG) Mode, page 36 for more information.
SelectIO Signal Standards
The IOBs support 17 different single-ended signal stan-
dards, as listed in Table 4. Furthermore, the majority of
IOBs can be used in specific pairs supporting any of six dif-
ferential signal standards, as shown in Table 5. The desired
standard is selected by placing the appropriate I/O library
symbol or component into the FPGA design. For example,
the symbol named IOBUF_LVCMOS15_F_8 represents a
bidirectional I/O to which the 1.5V LVCMOS signal standard
has been assigned. The slew rate and current drive are set
to Fast and 8 mA, respectively.
Together with placing the appropriate I/O symbol, two exter-
nally applied voltage levels, VCCO and VREF select the
desired signal standard. The VCCO lines provide current to
the output driver. The voltage on these lines determines the
4
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DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
11 Page | ||
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