PDF 74HC164 Data sheet ( Hoja de datos )

Número de pieza	74HC164
Descripción	8-Bit Serial-in/Parallel-out Shift Register
Fabricantes	Fairchild
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No Preview Available ! September 1983 Revised February 1999 MM74HC164 8-Bit Serial-in/Parallel-out Shift Register General Description The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low con- sumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices. This 8-Bit shift register has gated serial inputs and CLEAR. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-Bit register during the positive going transi- tion of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by inter- nal diode clamps to VCC and ground. Features s Typical operating frequency: 50 MHz s Typical propagation delay: 19 ns (clock to Q) s Wide operating supply voltage range: 2–6V s Low input current: 1 µA maximum s Low quiescent supply current: 80 µA maximum (74HC Series) s Fanout of 10 LS-TTL loads Ordering Code: Order Number Package Number Package Description MM74HC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74HC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC and TSSOP Inputs Clear Clock A L XX H LX H ↑H H ↑L H ↑X Outputs B QA QB ... XL L X QAO QBO H H QAn X L QAn L L QAn QH L QHO QGn QGn QGn H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW-to-HIGH level. QAO, QBO, QHO = the level of QA, QB, or QH, respectively, before the indi- cated steady state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicated a one-bit shift. Top View © 1999 Fairchild Semiconductor Corporation DS005315.prf www.fairchildsemi.com 1 page Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 5 www.fairchildsemi.com 5 Page

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