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PDF 29W040 Data sheet ( Hoja de datos )

Número de pieza 29W040
Descripción 4 Mbit 512Kb x8 / Uniform Block Low Voltage Single Supply Flash Memory
Fabricantes STMicroelectronics 
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M29W040
4 Mbit (512Kb x8, Uniform Block)
Low Voltage Single Supply Flash Memory
M29W040 is replaced by the M29W040B
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
BYTE PROGRAMMING TIME: 12µs typical
ERASE TIME
– Block: 1.5 sec typical
– Chip: 2.5 sec typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Data Polling and Toggle bits Protocol for
P/E.C. Status
MEMORY ERASE in BLOCKS
– 8 Uniform Blocks of 64 KBytes each
– Block Protection
– Multiblock Erase
ERASE SUSPEND and RESUME MODES
LOW POWER CONSUMPTION
– Read mode: 8mA typical (at 12MHz)
– Stand-by mode: 20µA typical
– Automatic Stand-by mode
POWER DOWN SOFTWARE COMMAND
– Power-down mode: 1µA typical
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: E3h
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7 Data Input / Outputs
E Chip Enable
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
NOT FOR NEW DESIGN
PLCC32 (K)
TSOP32 (N)
8 x 20mm
TSOP32 (NZ)
8 x 14mm
Figure 1. Logic Diagram
VCC
19
A0-A18
8
DQ0-DQ7
W M29W040
E
G
VSS
AI02074
November 1999
This is information on a product still in productionbut not recommended for new designs.
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29W040 pdf
M29W040
Table 6. Instructions (1)
Mne.
Instr. Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
RST (3,9)
Read Array/
Reset
Addr. (2,6)
X
1+ Read Memory Array until a new write cycle is initiated.
Data
F0h
Addr. (2,6) 5555h
3+
Data
AAh
2AAAh
55h
5555h Read Memory Array until a new write
cycle is initiated.
F0h
Read
RSIG (3) Electronic
Signature
Addr. (2,6) 5555h
3+
Data
AAh
2AAAh
55h
5555h Read Electronic Signature until a new
write cycle is initiated. See Note 4.
90h
RBP (3)
Read Block
Protection
Addr. (2,6) 5555h
3+
Data
AAh
2AAAh
55h
5555h Read Block Protection until a new write
cycle is initiated. See Note 5.
90h
PG Program
Addr. (2,6) 5555h
4
Data
AAh
2AAAh
55h
5555h
A0h
Program
Address Read Data Polling or Toggle Bit
until Program completes.
Program
Data
BE Block Erase
Addr. (2,6) 5555h
6
2AAAh
5555h
5555h
2AAAh
Block Additional
Address Block (7)
Data
AAh 55h 80h AAh 55h 30h
30h
CE Chip Erase
Addr. (2,6) 5555h
6
Data
AAh
2AAAh
55h
5555h
80h
5555h
AAh
2AAAh
55h
5555h
10h
Note 8
ES
Erase
Suspend
Addr. (2,6)
1
X
Read until Toggle stops, then read all the data needed from any
uniform block(s) not being erased then Resume Erase.
Data
B0h
ER
Erase
Resume
Addr. (2,6)
1
X
Read Data Polling or Toggle Bit until Erase completes or Erase
is suspended another time
Data
30h
PD (10)
Power
Down
1
Addr. (2,6) 5555h Puts the memory in Power Down mode where power
consumption is reduced to typically less than 1µA
Data
20h
Notes: 1. Command not interpreted in this table will default to read array mode.
2. X = Don’t Care.
3. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or
Electronic Signature codes. Any number of read cycles can occur after one command cycle.
4. Signature Address bits A0, A1, A6 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, A6 at VIL will output
Device code.
5. Protection Address: A0, A6 at VIL, A1 at VIH and A16, A17, A18 within the uniform block to be checked, will output the
Block Protection status.
6. Address bits A15-A18 are don’t care for coded address inputs.
7. Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verified
through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
8. Read Data Polling or Toggle bit until Erase completes.
9. A wait time of 5µs is necessary after a Reset command, if the memory is in a Block Erase or Power Down status, before
starting any operation.
10. Writing an RST command to the P/E.C. is mandatory prior to any new operation when the memory is in Power Down mode.
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29W040 arduino
M29W040
Table 12B. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
Symbol Alt
Parameter
Test Condition
-150
-200
Unit
VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V
Min Max Min Max
tAVAV
tRC
Address Valid to Next Address
Valid
E = VIL, G = VIL
150
200 ns
tAVQV tACC Address Valid to Output Valid
E = VIL, G = VIL
150
200 ns
tELQX (1)
tLZ
Chip Enable Low to Output
Transition
G = VIL
0
0 ns
tELQV (2) tCE Chip Enable Low to Output Valid
G = VIL
150 200 ns
tGLQX (1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
0
0 ns
tGLQV (2)
tOE
Output Enable Low to Output
Valid
E = VIL
55 70 ns
tEHQX
tEHQZ (1)
tGHQX
tOH
Chip Enable High to Output
Transition
tHZ Chip Enable High to Output Hi-Z
tOH
Output Enable High to Output
Transition
G = VIL
G = VIL
E = VIL
0 0 ns
40 50 ns
0 0 ns
tGHQZ (1)
tDF
Output Enable High to Output
Hi-Z
E = VIL
40 50 ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
0
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
0
ns
Read Array/Reset (RST) instruction. The Reset
instruction consists of one write operation giving
the command F0h. It can be optionally preceded
by the two coded cycles. A wait state of 5µs before
read operationsis necessaryif the Reset command
is applied during an Erase or Power Down opera-
tion.
Read Electronic Signature (RSIG) instruction.
This instruction uses the two coded cycles followed
by one write cycle giving the command 90h to
address 5555h for command setup. A subsequent
read will output the manufacturer code, the device
code or the Block Protection status depending on
the levels of A0, A1, A6, A16, A17 and A18. The
manufacturer code, 20h, is output when the ad-
dresses lines A0, A1 and A6 are Low, the device
code, E2h is output when A0 is High with A1 and
A6 Low.
Read Block Protection (RBP) instruction. The
use of Read ElectronicSignature(RSIG) command
also allows access to the Block Protection status
verify. After giving the RSIG command, A0 and A6
are set to VIL with A1 at VIH, while A16, A17 and
A18 define the block of the block to be verified. A
read in these conditions will output a 01h if block is
protected and a 00h if block is not protected.
This Read Block Protection is the only valid way to
check the protection status of a block. Neverthe-
less, it must not be used during the block protection
phase as a method to verify the Block Protection.
Please refer to Block Protection paragraph.
Power Down (PD) instruction. The Power Down
instruction uses one write cycle to put the memory
into a power down mode where current consump-
tion is typically reduced to less than 1.0µA. Once
in this state, a Reset (RST) command must be
written to the P/E.C. prior to any operation.
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