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PDF 29F010 Data sheet ( Hoja de datos )
| Número de pieza | 29F010 | |
| Descripción | 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only / Uniform Sector Flash Memory | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
Am29F010
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation
— 5.0 V ± 10% for read, erase, and program
operations
— Simplifies system-level power requirements
s High performance
— 45 ns maximum access time
s Low power consumption
— 30 mA max active read current
— 50 mA max program/erase current
— <25 µA typical standby current
s Flexible sector architecture
— Eight uniform sectors
— Any combination of sectors can be erased
— Supports full chip erase
s Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
s Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
s Minimum 100,000 program/erase cycles
guaranteed
s Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
Publication# 16736 Rev: G Amendment/+2
Issue Date: March 1998
1 page  
PIN CONFIGURATION
A0–A16 = 17 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE#
= Chip Enable
OE#
= Output Enable
WE#
= Write Enable
VCC = +5.0 Volt Single Power Supply
(See Product Selector Guide for speed
options and voltage supply tolerances)
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
17
A0–A16
CE#
OE#
WE#
DQ0–DQ7
8
16736G-6
Am29F010
5
5 Page 
START
Write Program
Command Sequence
Embedded
Program
algorithm
in progress
Data Poll
from System
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
16736G-7
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored.
The system can determine the status of the erase
operation by using DQ7 or DQ6. See “Write Opera-
tion Status” for information on these status bits.
When the Embedded Erase algorithm is complete,
the device returns to reading array data and ad-
dresses are no longer latched.
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the ad-
dress of the sector to be erased, and the sector erase
command. The Command Definitions table shows the
address and data requirements for the sector erase
command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
Am29F010
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 29F010.PDF ] | |
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