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PDF 29102BJA Data sheet ( Hoja de datos )

Número de pieza 29102BJA
Descripción 2K x 8 CMOS RAM
Fabricantes Intersil 
Logotipo Intersil Logotipo



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HM-6516
March 1997
2K x 8 CMOS RAM
Features
Description
• Low Power Standby . . . . . . . . . . . . . . . . . . . 275µW Max
• Low Power Operation . . . . . . . . . . . . . 55mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• Industry Standard Pinout
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC
• TTL Compatible
• Static Memory Cells
• High Output Drive
• On-Chip Address Latches
• Easy Microprocessor Interfacing
The HM-6516 is a CMOS 2048 x 8 Static Random Access
Memory. Extremely low power operation is achieved by the
use of complementary MOS design techniques. This low
power is further enhanced by the use of synchronous circuit
techniques that keep the active (operating) power low, which
also gives fast access times. The pinout of the HM-6516 is
the popular 24 pin, 8-bit wide JEDEC standard, which allows
easy memory board layouts, flexible enough to accommo-
date a variety of PROMs, RAMS, EPROMs, and ROMs.
The HM-6516 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum, because only one device is enabled at a time. The
address latches allow very simple interfacing to recent gen-
eration microprocessors which employ a multiplexed
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.
Ordering Information
120ns
HM1-6516B-9
-
8403607JA
-
8403607ZA
Pinouts
HM-6516
(CERDIP)
TOP VIEW
200ns
HM1-6516-9
29102BJA
8403601JA
HM4-6516-9
8403601ZA
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
PACKAGE
CERDIP
JAN#
SMD#
CLCC
SMD#
HM-6516
(CLCC)
TOP VIEW
PKG. NO.
F24.6
F24.6
F24.6
J32.A
J32.A
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
DQ0 9
DQ1 10
DQ2 11
GND 12
24 VCC
23 A8
22 A9
21 W
20 G
19 A10
18 E
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
26 W
A2 9
25 G
A1 10
24 A10
A0 11
23 E
NC 12
22 DQ7
DQ0 13
21 DQ6
14 15 16 17 18 19 20
PIN DESCRIPTION
NC No Connect
A0 - A10 Address Inputs
E Chip Enable/Power Down
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
VCC
W
Power (+5V)
Write Enable
G Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 2998.1

1 page




29102BJA pdf
HM-6516
Timing Waveforms
(11)
A
TAVEL
(2)
TAVQV
(12)
TELAX
VALID ADD
(10)
TEHEL
E
HIGH
W
(5)
TEHQZ
DQ
G
(9)
TELEH
(1)
(3) TELQV
TELQX
(6)
TGLQV
(7)
TGLQX
(18)
TELEL
(11)
TAVEL
NEXT
ADD
(10)
TEHEL
(5)
TEHQZ
VALID DATA OUT
TGHQZ
(8)
TIME
REFERENCE
-1 0
1 23 4 5
FIGURE 1. READ CYCLE
The address information is latched in the on-chip registers
on the falling edge of E (T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1), the outputs become
enabled but data is not valid until time (T = 2), W must
remain high throughout the read cycle. After the data has
been read, E may return high (T = 3). This will force the out-
put buffers into a high impedance mode at time (T = 4). G is
used to disable the output buffers when in a logical “1” state
(T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for
the next cycle.
Timing Waveforms (Continued)
(11)
TAVEL
(12)
TELAX
(11)
TAVEL
A VALID ADD
NEXT ADD
(10)
TEHEL
(9)
TELEH
(18)
TELEL
(10)
TEHEL
E
(14)
TWLEH
(13)
TWLWH
W
(15)
TELWH
(16)
TDVWH
(17)
TWHDX
DQ
G HIGH
VALID DATA IN
TIME
REFERENCE
-1 0
1
23
4
5
FIGURE 2. WRITE CYCLE
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