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PDF 28F800F3 Data sheet ( Hoja de datos )

Número de pieza 28F800F3
Descripción 3 Volt Fast Boot Block Flash Memory
Fabricantes Intel 
Logotipo Intel Logotipo



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3 Volt Fast Boot Block Flash Memory
28F800F3—Automotive
Preliminary Datasheet
Product Features
s High Performance
Up to 50 MHz Effective Zero Wait-State
Performance
Synchronous Burst-Mode Reads
Asynchronous Page-Mode Reads
s SmartVoltage Technology
3.0 V3.6 V Read and Write Operations for
Low Power Designs
12 V VPP Fast Factory Programming
s Enhanced Data Protection
Absolute Write Protection with
VPP = GND
Block Locking
Block Erase/Program Lockout during Power
Transitions
s Manufactured on ETOXV Flash Technology
s Supports Code Plus Data Storage
Optimized for Flash Data Integrator (FDI)
and other Intel® Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
s Flexible Blocking Architecture
Eight 4-Kword Blocks for Data
32-Kword Main Blocks for Code
Top or Bottom Boot Configurations
s Extended Cycling Capability
s Low Power Consumption
s Automated Program and Block Erase
Algorithms
Command User Interface for Automation
Status Register for System Feedback
s Industry-Standard Packaging
56-Lead SSOP
Intel® Easy BGA
The Intel® 3 Volt Fast Boot Block Flash memory offers the highest performance synchronous burst reads
making it an ideal memory solution for burst CPUs. The Intel 3 Volt Fast Boot Block Flash memory also
supports asynchronous page mode operation for non-clocked memory subsystems. Combining high read
performance with the intrinsic nonvolatility of flash memory eliminates the traditional redundant memory
paradigm of shadowing code from a slower nonvolatile storage source to a faster execution memory device,
(e.g., SRAM SDRAM), for improved system performance. By adding 3 Volt Fast Boot Block Flash
memory to your system you could reduce the total memory requirement, which helps increase reliability
and reduce overall system power consumptionall while reducing system cost.
This family of products is manufactured on Intel® 0.4 µm ETOXV process technology. They are
available in a wide variety of industry-standard packaging technologies.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290686-003
March 2001

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28F800F3 pdf
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228F800F3Automotive
Revision History
Date of
Revision
10/01/99
08/03/00
03/26/01
Version
-001
-002
-003
Description
Original version
Removed all references to 5 V and 1.65 V I/O capability.
Removed -125 ns device and added 80ns device.
Changed tCHQV time from 19 ns to 17 ns.
Changed tAPA time from 35 ns to 25 ns.
Changed tEHQZ/GHQV time from 25 ns to 23 ns.
Changed tDVWH time from 70 ns to 63 ns.
Changed block program and erase times in Table 8.8.
Minor text edits.
Changed tCHQV time
teristics—Read-Only
for 95 device from 10ns to 19ns in Table 8.5,
Operations (1,2) —Automotive Temperature
AC
Charac-
Revised Table 8.8, Automotive Temperature Block Erase and Program
Performance (1,2,3)
PRELIMINARY
v

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28F800F3 arduino
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28F800F3Automotive
Table 1. Pin Descriptions (Sheet 2 of 2)
Sym
Type
WE#
INPUT
WP#
INPUT
WAIT# OUTPUT
VPP SUPPLY
VCC
VCCQ
GND
NC
SUPPLY
SUPPLY
SUPPLY
Name and Function
WRITE ENABLE: Controls writes to the CUI and array. Addresses and data are latched on the rising
edge of the WE# pulse.
WRITE PROTECTION: Provides a method for locking and unlocking all main blocks and two
parameter blocks.
When WP# is at logic low, lockable blocks are locked. If a program or erase operation is attempted on
a locked block, SR.1 and either SR.4 [program] or SR.5 [block erase] will be set to indicate the
operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.
WAIT: Provides data valid feedback only when configured for synchronous burst mode and the burst
length is set to continuous. This signal is gated by OE# and CE# and is internally pull-up to VCCQ via a
resistor. WAIT# from several components can be tied together to form one system WAIT# signal.
BLOCK ERASE AND PROGRAM POWER SUPPLY (3.0 V–3.6 V, 11.4 V–12.6 V): For erasing array
blocks or programming data, a valid voltage must be applied to this pin. With VPP VPPLK, memory
contents cannot be altered. Block erase and program with an invalid VPP voltage should not be
attempted.
Applying 11.4 V12.6 V to VPPcan only be done for a maximum of 1000 cycles on main blocks and
2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum
(see Section 6.0 for details).
DEVICE POWER SUPPLY (3.0 V3.6 V): With VCC VLKO, all write attempts to the flash memory are
inhibited. Device operations at invalid VCC voltages should not be attempted.
OUTPUT POWER SUPPLY (3.0 V3.6 V): Enables all outputs to be driven to 3.0 V to 3.6 V.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated. (Pins noted as possible
upgrades to 32-Mbit and 64-Mbit densities can be connected to the appropriate address lines to pre-
enable designs for possible future devices.).
2.3
2.3.1
2.3.2
Memory Blocking Organization
The 3 Volt Fast Boot Block Flash memory family is an asymmetrically-blocked architecture that
enables system integration of code and data within a single flash device. For the address locations
of each block, see the memory maps in Figure 3, 8- Mbit Top Boot and Bottom Boot Memory
Mapon page 6. 8-Mbit Top Boot and Bottom Boot Blocking.
Parameter Blocks
The 3 Volt Fast Boot Block Flash memory architecture includes parameter blocks to facilitate
storage of frequently updated small parameters that would normally be stored in an EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each
8- Mbit device contains eight 4-Kwords (4,096-words) parameter blocks.
Main Blocks
After the parameter blocks, the remainder of the array is divided into equal size main blocks for
code and/or data storage. The main blocks are the area of the device that support four-, eight-, and
continuous burst operations. The 8-Mbit device contains fifteen 32-Kword (32,768-word) main
blocks.
PRELIMINARY
5

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