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PDF 28F400B3 Data sheet ( Hoja de datos )

Número de pieza 28F400B3
Descripción SMART 3 ADVANCED BOOT BLOCK WORD-WIDE
Fabricantes Intel 
Logotipo Intel Logotipo



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E
PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
WORD-WIDE
4-MBIT (256K X 16), 8-MBIT (512K X 16),
16-MBIT (1024K X 16)
FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3
n Flexible SmartVoltage Technology
2.7V–3.6V Program/Erase
2.7V–3.6V Read Operation
12V VPP Fast Production
Programming
n 2.7V or 1.8V I/O Option
Reduces Overall System Power
n Optimized Block Sizes
Eight 4-KW Blocks for Data,
Top or Bottom Locations
Up to Thirty-One 32-KW Blocks for
Code
n High Performance
2.7V–3.6V: 120 ns Max Access Time
n Block Locking
VCC-Level Control through WP#
n Low Power Consumption
20 mA Maximum Read Current
n Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n Extended Temperature Operation
–40°C to +85°C
n Supports Code Plus Data Storage
Optimized for FDI, Flash Data
Integrator Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n Extended Cycling Capability
10,000 Block Erase Cycles
n Automated Word Program and Block
Erase
Command User Interface
Status Registers
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
n Reset/Deep Power-Down
1 µA ICCTypical
Spurious Write Lockout
n Standard Surface Mount Packaging
48-Ball µBGA* Package
48-Lead TSOP Package
n Footprint Upgradeable
Upgradeable from 2-, 4- and 8-Mbit
Boot Block
n ETOX™ V (0.4 µ) Flash Technology
The new Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.4µ technology, represents a feature-
rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.8V, which significantly reduces system active power and
interfaces to 1.8V controllers. A new blocking scheme enables code and data storage within a single device.
Add to this the Intel-developed Flash Data Integrator (FDI) software and you have the most cost-effective,
monolithic code plus data storage solution on the market today. Smart 3 Advanced Boot Block Word-Wide
products will be available in 48-lead TSOP and 48-ball µBGA* packages. Additional information on this
product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp.
May 1997
Order Number: 290580-002

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28F400B3 pdf
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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
1.0 INTRODUCTION
This preliminary datasheet contains the
specifications for the Advanced Boot Block flash
memory family, which is optimized for low power,
portable systems. This family of products features
1.8V–2.2V or 2.7V–3.6V I/Os and a low VCC/VPP
operating range of 2.7V–3.6V for read and
program/erase operations. In addition this family is
capable of fast programming at 12V. Throughout
this document, the term “2.7V” refers to the full
voltage range 2.7V–3.6V (except where noted
otherwise) and “VPP = 12V” refers to 12V ±5%.
Section 1 and 2 provides an overview of the flash
memory family including applications, pinouts and
pin descriptions. Section 3 describes the memory
organization and operation for these products.
Finally, Sections 4, 5, 6 and 7 contain the
operating specifications.
1.1 Smart 3 Advanced Boot Block
Flash Memory Enhancements
The new 4-Mbit, 8-Mbit, and 16-Mbit Smart 3
Advanced Boot Block flash memory provides a
convenient upgrade from and/or compatibility to
previous 4-Mbit and 8-Mbit Boot Block products.
The Smart 3 product functions are similar to lower
density products in both command sets and
operation, providing similar pinouts to ease density
upgrades.
The Smart 3 Advanced Boot Block flash memory
features
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
Program Suspend command which permits
program suspend to read
WP# pin to lock and unlock the upper two (or
lower two, depending on location) 4-Kword
blocks
VCCQ input for 1.8V–2.2V on all I/Os. See
Figure 1-4 for pinout diagrams and VCCQ
location
Maximum program time specification for
improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature
28F160B3
VCC Read Voltage
2.7V– 3.6V
VCCQ I/O Voltage
1.8V–2.2V or 2.7V– 3.6V
VPP Program/Erase Voltage 2.7V– 3.6V or 11.4V– 12.6V
Bus Width
16 bit
Speed
120 ns
Memory Arrangement
256-Kbit x 16 (4-Mbit), 512-Kbit x 16 (8-Mbit),
1024-Kbit x 16 (16-Mbit)
Blocking (top or bottom)
Eight 4-Kword parameter blocks (4/8/16) &
Seven 32-Kword blocks (4-Mbit)
Fifteen 32-Kword blocks (8-Mbit)
Thirty-one 32-Kword main blocks (16-Mbit)
Locking
WP# locks/unlocks parameter blocks
All other blocks protected using VPP switch
Operating Temperature
Extended: –40°C to +85°C
Program/Erase Cycling
10,000 cycles
Packages
48-Lead TSOP, 48-Ball µBGA* CSP
Reference
Table 9, Table 12
Table 9, Table 12
Table 9, Table 12
Table 2
Table 15
Section 2.2
Figures 5 and 6
Section 3.3
Table 8
Table 9, Table 12
Table 9, Table 12
Figures 1, 2, 3,
and 4
PRELIMINARY
5

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28F400B3 arduino
E
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued)
Symbol
Type
Name and Function
VCCQ
INPUT
OUTPUT VCC: Enables all outputs to be driven to 2.0V ±10% while the
VCC is at 2.7V. When this mode is used, the VCC should be regulated to
2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC
Characteristics: VCCQ = 1.8V–2.2V).
This input may be tied directly to VCC (2.7V–3.6V).
See the DC Characteristics for further details.
VCC DEVICE POWER SUPPLY: 2.7V–3.6V
VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array
blocks or programming data in each block, a voltage of either 2.7V–3.6V
or 12V ± 5% must be applied to this pin. When VPP < VPPLK all blocks
are locked and protected against Program and Erase commands.
Applying 11.4V-12.6V to VPP can only be done for a maximum of 1000
cycles on the main blocks and 2500 cycles on the parameter blocks.
VPP may be connected to 12V for a total of 80 hours maximum (see
Section 3.4 for details).
GND
GROUND: For all internal circuitry. All ground inputs must be
connected.
NC NO CONNECT: Pin may be driven or left floating.
2.2 Block Organization
The Smart 3 Advanced Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. Each block can be erased
independently of the others up to 10,000 times. For
the address locations of each block, see the
memory maps in Figure 5 (top boot blocking) and
Figure 6 (bottom boot blocking).
2.2.1
PARAMETER BLOCKS
The Smart 3 Advanced Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(e.g., data that would normally be stored in an
EEPROM). By using software techniques, the word-
rewrite functionality of EEPROMs can be emulated.
Each 4-/8-/16-Mbit device contains eight parameter
blocks of 4-Kwords (4,096-words) each.
2.2.2
MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal size main blocks for data
or code storage. Each 16-Mbit device contains
thirty-one 32-Kword (32,768-word) blocks. Each
8-Mbit device contains fifteen 32-Kword blocks.
Each 4-Mbit device contains seven 32-Kword
blocks.
PRELIMINARY
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