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PDF 28F320J5 Data sheet ( Hoja de datos )

Número de pieza 28F320J5
Descripción StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
Fabricantes Intel 
Logotipo Intel Logotipo



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ADVANCE INFORMATION
INTEL StrataFlash™ MEMORY TECHNOLOGY
32 AND 64 MBIT
28F320J5 and 28F640J5
n High-Density Symmetrically-Blocked
Architecture
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
n 5 V VCC Operation
2.7 V I/O Capable
n Configurable x8 or x16 I/O
n 120 ns Read Access Time (32 M)
150 ns Read Access Time (64 M)
n Enhanced Data Protection Features
Absolute Protection with
VPEN = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Industry-Standard Packaging
µBGA* Package, SSOP and TSOP
Packages (32 M)
n Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
Scaleable Command Set
n 32-Byte Write Buffer
6 µs per Byte Effective
Programming Time
n 640,000 Total Erase Cycles (64 M)
320,000 Total Erase Cycles (32 M)
10,000 Erase Cycles per Block
n Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
n System Performance Enhancements
STS Status Output
n Intel StrataFlash™ Memory Flash
Technology
Capitalizing on two-bit-per-cell technology, Intel StrataFlash™ memory products provide 2X the bits in 1X the
space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are
the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result,
Intel StrataFlash components are ideal for code or data applications where high density and low cost are
required. Examples include networking, telecommunications, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5
and 28F320S5).
Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel’s 0.4 micron ETOX™ V process technology, Intel StrataFlash memory provides the
highest levels of quality and reliability.
January 1998
Order Number: 290606-004

1 page




28F320J5 pdf
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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
1.0 PRODUCT OVERVIEW
The Intel StrataFlash™ memory family contains
high-density memories organized as 8 Mbytes or
4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords
(32-Mbit). These devices can be accessed as 8- or
16-bit words. The 64-Mbit device is organized as
sixty-four 128-Kbyte (131,072 bytes) erase blocks
while the 32-Mbits device contains thirty-two 128-
Kbyte erase blocks. Blocks are selectively and
individually lockable and unlockable in-system.
See the memory map in Figure 5.
A Common Flash Interface (CFI) permits software
algorithms to be used for entire families of
devices. This allows device-independent, JEDEC
ID-independent, and forward- and backward-
compatible software support for the specified flash
device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board place-
ment). Additionally, SCS provides the highest
system/device data transfer rates and minimizes
device and system-level implementation costs.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for block erase, program, and
lock-bit configuration operations.
A block erase operation erases one of the device’s
128-Kbyte blocks typically within one second—
independent of other blocks. Each block can be
independently erased 10,000 times. Block erase
suspend mode allows system software to suspend
block erase to read or program data from any
other block.
Each device incorporates a Write Buffer of
32 bytes (16 words) to allow optimum
programming performance. By using the Write
Buffer, data is programmed in buffer increments.
This feature can improve system program
performance by up to 20 times over non Write
Buffer writes.
Individual block locking uses a combination of bits,
block lock-bits and a master lock-bit, to lock and
unlock blocks. Block lock-bits gate block erase
and program operations while the master lock-bit
gates block lock-bit modification. Three lock-bit
configuration operations set and clear lock-bits
(Set Block Lock-Bit, Set Master Lock-Bit, and
Clear Block Lock-Bits commands).
The status register indicates when the WSM’s
block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional
indicator of WSM activity by providing both a
hardware signal of status (versus software polling)
and status masking (interrupt masking for
background block erase, for example). Status
indication using STS minimizes both CPU
overhead and system power consumption. When
configured in level mode (default mode), it acts as
a RY/BY# pin. When low, STS indicates that the
WSM is performing a block erase, program, or
lock-bit configuration. STS-high indicates that the
WSM is ready for a new command, block erase is
suspended (and programming is inactive), or the
device is in reset/power-down mode. Additionally,
the configuration command allows the STS pin to
be configured to pulse on completion of
programming and/or block erases.
Three CE pins are used to enable and disable the
device. A unique CE logic design (see Table 2,
Chip Enable Truth Table) reduces decoder logic
typically required for multi-chip designs. External
logic is not required when designing a single chip,
a dual chip, or a 4-chip miniature card or SIMM
module.
The BYTE# pin allows either x8 or x16 read/writes
to the device. BYTE# at logic low selects 8-bit
mode; address A0 selects between the low byte
and high byte. BYTE# at logic high enables 16-bit
operation; address A1 becomes the lowest order
address and address A0 is not used (don’t care). A
device block diagram is shown in Figure 1.
When the device is disabled (see Table 2, Chip
Enable Truth Table) and the RP# pin is at VCC, the
standby mode is enabled. When the RP# pin is at
GND, a further power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV)
is required from RP# switching high until outputs
ADVANCE INFORMATION
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5 Page





28F320J5 arduino
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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
0606_04
NOTE:
VCC (Pin 42) and GND (Pin 15) are not internally connected. For future device revisions, it is recommended that these pins be
connected to their respected power supplies (i.e., Pin 42 = VCC and Pin 15 = GND).
Figure 4. SSOP Lead Configuration (64 Mbit and 32 Mbit)
2.0 PRINCIPLES OF OPERATION
The Intel StrataFlash memory devices include an
on-chip WSM to manage block erase, program, and
lock-bit configuration functions. It allows for 100%
TTL-level control inputs, fixed power supplies
during block erasure, program, lock-bit
configuration, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from
reset/power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of
external memory control pins allows array read,
standby, and output disable operations.
Read array, status register, query, and identifier
codes can be accessed through the CUI (Command
User Interface) independent of the VPEN voltage.
ADVANCE INFORMATION
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