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PDF 28F200B5 Data sheet ( Hoja de datos )

Número de pieza 28F200B5
Descripción SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2 / 4 / 8 MBIT
Fabricantes Intel 
Logotipo Intel Logotipo



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E
ADVANCE INFORMATION
SMART 5 BOOT BLOCK
FLASH MEMORY FAMILY
2, 4, 8 MBIT
28F200B5, 28F400B5, 28F800B5, 28F004B5
n SmartVoltage Technology
Smart 5 Flash: 5 V Reads,
5 V or 12 V Writes
Increased Programming Throughput
at 12 V VPP
n Very High-Performance Read
2-, 4-Mbit: 60 ns Access Time
8-Mbit: 70 ns Access Time
n x8 or x8/x16-Configurable Data Bus
n Low Power Consumption
Max 60 mA Read Current at 5 V
Auto Power Savings: <1 mA Typical
Standby Current
n Optimized Array Blocking Architecture
16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
n Extended Temperature Operation
–40 °C to +85 °C
n Industry-Standard Packaging
40, 48-Lead TSOP, 44-Lead PSOP
n Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
n Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Reset/Deep Power-Down Input
Provides Low-Power Mode and
Reset for Boot Operations
n Pinout Compatible 2, 4, and 8 Mbit
n ETOX™ Flash Technology
0.6 µ ETOX IV Initial Production
0.4 µ ETOX V Later Production
Intel’s Smart 5 boot block flash memory family provides 2-, 4-, and 8-Mbit memories featuring high-density,
low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their asymmetrically-
blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for
embedded code execution applications, such as networking infrastructure and office automation.
Based on Intel’s boot block architecture, the Smart 5 boot block memory family enables quick and easy
upgrades for designs that demand state-of-the-art technology. This family of products comes in industry-
standard packages: the 40-lead TSOP for very space-constrained 8-bit applications, 48-lead TSOP, ideal for
board-constrained higher-performance 16-bit applications, and the rugged, easy to handle 44-lead PSOP.
December 1997
Order Number: 290599-004

1 page




28F200B5 pdf
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SMART 5 BOOT BLOCK MEMORY FAMILY
1.0 INTRODUCTION
This datasheet contains specifications for 2-, 4-,
and 8-Mbit Smart 5 boot block flash memories.
Section 1.0 provides a feature overview. Sections
2.0, 3.0, and 4.0 describe the product and
functionality. Section 5.0 details the electrical and
timing specifications for both commercial and
extended temperature operation. Finally, Sections
6.0 and 7.0 provide ordering and reference
information.
A delay is required if the part is reset during an
in-progress program or erase operation.
On the fly word-byte mode switching is no
longer supported. Word-byte mode must be
configured at power-up and remain stable
during operation.
Write operations are no longer specified as
WE#- or CE#-controlled in favor of a simpler
“unified” write method, which is compatible
with either of the old methods.
1.1 New Features in the
Smart 5 Memory Products
The Smart 5 boot block flash memory family offers
identical features with the BV/CV/BE/CE
SmartVoltage products, except the Smart 5 boot
block -B5 parts only support 5 V VCC read voltage.
The following differences distinguish the Smart 5
boot block products from their predecessors:
1.2 Product Overview
The Smart 5 boot block memory family provides
pinout-compatible flash memories at the
2-, 4-, and 8-Mbit densities. The 28F200B5,
28F400B5, and 28F800B5 can be configured to
operate either in 16-bit or 8-bit bus mode, with the
data divided into individually erasable blocks. The
28F004B5 provides 8-bit operation in a compact
package.
Table 1. Smart 5 Boot Block Family: Feature Summary
Feature
28F200B5
28F400B5
28F800B5
28F004B5 Reference
VCC Read Voltage
5 V ± 5%, 5 V ± 10%
Section 5.2
VPP Prog/Erase Voltage
5 V ± 10% or 12 V ± 5%, auto-detected
Section 5.2
Bus-width
8- or 16-bit
8- or 16-bit
8- or 16-bit
8-bit
Table 2
Speed (ns) Commercial
60, 80
70, 90
60, 80
Section 5.6
Extended
80
80
90 not available Section 5.6
Memory Arrangement
x8: 256K x 8 x8: 512K x 8 x8: 1M x 8 x8: 512K x 8
x16: 128K x 16 x16: 256K x 16 x16: 512K x 16
Blocking Boot
1 x 16 KB
1 x 16 KB
1 x 16 KB
1 x 16 KB Section 2.3,
Parameter
2 x 8 KB
2 x 8 KB
2 x 8 KB
2 x 8 KB Figs. 4-7
Main
1 x 96 KB
1 x 128 KB
1 x 96 KB
3 x 128 KB
1 x 96 KB
7 x 128 KB
1 x 96 KB
3 x 128 KB
Boot Location
Top or Bottom boot locations available
Locking
Boot Block lockable using WP# and/or RP#
All other blocks protectable using VPP switch
Section 3.3
Operating Temperature
Commercial: 0 °C – +70 °C, Extended: -40 °C – +85 °C
Section 5.2
Erase Cycling
100,000 cycles at Commercial, 10,000 cycles at Extended
Packages
44-PSOP, 48-TSOP
40-TSOP Figs. 1-2
ADVANCE INFORMATION
5

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28F200B5 arduino
E
SMART 5 BOOT BLOCK MEMORY FAMILY
1FFFFH
1E000H
1DFFFH
1D000H
1CFFFH
1C000H
1BFFFH
10000H
0FFFFH
00000H
28F200-T
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
3FFFFH
3E000H
3DFFFH
3D000H
3CFFFH
3C000H
3BFFFH
30000H
2FFFFH
20000H
1FFFFH
10000H
0FFFFH
00000H
28F400-T
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
NOTE: Word addresses shown.
7FFFFH
7E000H
7DFFFH
7D000H
7CFFFH
7C000H
7BFFFH
70000H
6FFFFH
60000H
5FFFFH
50000H
4FFFFH
40000H
3FFFFH
30000H
2FFFFH
20000H
1FFFFH
10000H
0FFFFH
00000H
28F800-T
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
0599-03
Figure 4. Word-Wide x16-Mode Memory Maps (Top Boot)
1FFFFH
10000H
0FFFFH
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
00000H
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
28F200-B
NOTE: Word addresses shown.
3FFFFH
30000H
2FFFFH
20000H
1FFFFH
10000H
0FFFFH
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
00000H
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
28F400-B
7FFFFH
70000H
6FFFFH
60000H
5FFFFH
50000H
4FFFFH
40000H
3FFFFH
30000H
2FFFFH
20000H
1FFFFH
10000H
0FFFFH
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
00000H
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
28F800-B
0599-04
Figure 5. Word-Wide x16-Mode Memory Maps (Bottom Boot)
ADVANCE INFORMATION
11

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