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PDF 28F160S5 Data sheet ( Hoja de datos )

Número de pieza 28F160S5
Descripción WORD-WIDE FlashFile MEMORY FAMILY
Fabricantes Intel 
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ADVANCE INFORMATION
WORD-WIDE
FlashFile™ MEMORY FAMILY
28F160S5, 28F320S5
Includes Extended Temperature Specifications
n Two 32-Byte Write Buffers
2 µs per Byte Effective
Programming Time
n Operating Voltage
5V VCC
5V VPP
n 70 ns Read Access Time (16 Mbit)
90 ns Read Access Time (32 Mbit)
n High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
n System Performance Enhancements
STS Status Output
n Industry-Standard Packaging
SSOP and TSOP (16 Mbit)
SSOP (32 Mbit)
n Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
n 100,000 Block Erase Cycles
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Configurable x8 or x16 I/O
n Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n ETOX™ V Nonvolatile Flash
Technology
Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, nonvolatile, read/write storage
solutions for a wide range of applications. The word-wide memories are available at various densities in the
same package type. Their symmetrically-blocked architecture, voltage, and extended cycling provide highly
flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend
capabilities provide an ideal solution for code or data storage applications. For secure code storage
applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM,
the word-wide memories offer three levels of protection: absolute protection with VPP at GND, selective block
locking, and program/erase lockout during power transitions. These alternatives give designers ultimate
control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the
industry-standard 56-lead SSOP. In addition, the 16-Mb device is available in the industry-standard 56-lead
TSOP package.
June 1997
Order Number: 290609-001

1 page




28F160S5 pdf
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28F160S5, 28F320S5
1.0 INTRODUCTION
This datasheet contains Word-Wide FlashFile™
memory (28F160S5, 28F320S5) specifications.
Section 1 provides a flash memory overview.
Sections 2, 3, 4, and 5 describe the memory
organization and functionality. Section 6 covers
electrical specifications for extended temperature
product offerings.
1.1 New Features
The Word-Wide FlashFile memory family maintains
basic compatibility with Intel’s 28F016SA and
28F016SV. Key enhancements include:
Common Flash Interface (CFI) Support
Scaleable Command Set (SCS) Support
S5 Technology
Enhanced Suspend Capabilities
They share a compatible Status Register, basic
software commands, and pinout. These similarities
enable a clean migration from the 28F016SA or
28F016SV. When upgrading, it is important to note
the following differences:
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
New software commands.
To take advantage of the 5V technology on the
28F160S5 and 28F320S5, allow VPP
connection to VCC. The 28F160S5 and
28F320S5 FlashFile memories do not support a
12V VPP option.
1.2 Product Overview
The Word-Wide FlashFile memory family provides
density upgrades with pinout compatibility for the
16- and 32-Mbit densities. They are high-
performance memories arranged as 1 Mword and
2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of
8 bits. This data is grouped in thirty-two and sixty-
four 64-Kbyte blocks that can be erased, locked,
and unlocked in-system. Figure 1 shows the block
diagram, and Figure 4 illustrates the memory
organization.
Specifically designed for 5V systems, the
28F160S5 and 28F320S5 support read and write
operation with VCC equal to VPP. Coupled with this
capability, high programming performance is
achieved through small, highly-optimized write
buffer operations. Additionally, the dedicated VPP
pin gives complete data protection when VPP
VPPLK.
A Common Flash Interface (CFI) permits OEM-
specified software algorithms to be used for entire
families of devices. This allows device-independent,
JEDEC ID-independent, and forward- and
backward-compatible software support for the
specified flash device families. Flash vendors can
standardize their existing interfaces for long-term
compatibility.
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement).
Additionally, SCS provides the highest
system/device data transfer rates and minimizes
device and system-level implementation costs.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal device operation. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within tWHQV2/EHQV2
independent of other blocks. Each block can be
independently erased 100,000 times. Block erase
suspend allows system software to suspend block
erase to read or write data from any other block.
Data is programmed in byte, word or page
increments. Program suspend mode enables the
system to read data or execute code from any other
flash memory array location.
The device incorporates two Write Buffers of 32
bytes (16 words) to allow optimum-performance
data programming. This feature can improve
system program performance by up to eight times
over non-buffer programming.
ADVANCE INFORMATION
5

5 Page





28F160S5 arduino
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3.0 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1 Read
Block information, query information, identifier
codes and Status Registers can be read
independent of the VPP voltage.
The first task is to place the device into the
desired read mode by writing the appropriate
read-mode command (Read Array, Query, Read
Identifier Codes, or Read Status Register) to the
CUI. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically resets to read array mode. Control
pins dictate the data flow in and out of the
component. CE0#, CE1# and OE# must be driven
active to obtain data at the outputs. CE0# and
CE1# are the device selection controls, and,
when both are active, enable the selected
memory device. OE# is the data output (DQ0
DQ15) control: When active it drives the selected
memory data onto the I/O bus. WE# must be at
VIH and RP# must be at VIH. Figure 16 illustrates
a read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
3.3 Standby
CE0# or CE1# at a logic-high level (VIH) places
the device in standby mode, substantially
reducing device power consumption. DQ0–DQ15
(or DQ0– DQ7 in x8 mode) outputs are placed in
a high-impedance state independent of OE#. If
deselected during block erase, programming, or
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
28F160S5, 28F320S5
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be
held low for time tPLPH. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI
resets to read array mode, and the Status
Register is set to 80H.
During block erase, programming, or lock-bit
configuration modes, RP#-low will abort the
operation. STS in RY/BY# mode remains low
until the reset operation is complete. Memory
contents being altered are no longer valid; the
data may be partially corrupted after
programming or partially altered after an erase or
lock-bit configuration. Time tPHWL is required after
RP# goes to logic-high (VIH) before another
command can be written.
It is important in any automated system to assert
RP# during system reset. When the system
comes out of reset, it expects to read from the
flash memory. Automated flash memories
provide status information when accessed during
block erase, programming, or lock-bit
configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization
may not occur because the flash memory may be
providing status information instead of array data.
Intel’s Flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that
resets the system CPU.
3.5 Read Query Operation
The read query operation outputs block status,
Common Flash Interface (CFI) ID string, system
interface, device geometry, and Intel-specific
extended query information.
ADVANCE INFORMATION
11

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