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PDF 28F160S3 Data sheet ( Hoja de datos )

Número de pieza 28F160S3
Descripción WORD-WIDE FlashFile MEMORY FAMILY
Fabricantes Intel 
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ADVANCE INFORMATION
WORD-WIDE
FlashFile™ MEMORY FAMILY
28F160S3, 28F320S3
Includes Extended Temperature Specifications
n Two 32-Byte Write Buffers
2.7 µs per Byte Effective
Programming Time
n Low Voltage Operation
2.7V or 3.3V VCC
2.7V, 3.3V or 5V VPP
n 100 ns Read Access Time (16 Mbit)
110 ns Read Access Time (32 Mbit)
n High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
n System Performance Enhancements
STS Status Output
n Industry-Standard Packaging
µBGA* package, SSOP, and
TSOP (16 Mbit)
µBGA* package and SSOP (32 Mbit)
n Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
n 100,000 Block Erase Cycles
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Configurable x8 or x16 I/O
n Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n ETOX™ V Nonvolatile Flash
Technology
Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, non-volatile, read/write storage
solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various
densities in the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended
cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards.
Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure
code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of protection: absolute protection
with VPP at GND, selective block locking, and program/erase lockout during power transitions. These
alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the
industry-standard 56-lead SSOP and µBGA packages. In addition, the 16-Mb device is available in the
industry-standard 56-lead TSOP package.
June 1997
Order Number: 290608-001

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28F160S3 pdf
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28F160S3, 28F320S3
1.0 INTRODUCTION
This datasheet contains 16- and 32-Mbit Word-
Wide FlashFileTM memory (28F160S3 and
28F320S3) specifications. Section 1 provides a
flash memory overview. Sections 2, 3, 4, and 5
describe the memory organization and functionality.
Section 6 covers electrical specifications for
extended temperature product offerings.
1.1 New Features
The Word-Wide FlashFile memory family maintains
basic compatibility with Intel’s 28F016SA and
28F016SV. Key enhancements include:
Common Flash Interface (CFI) Support
Scaleable Command Set (SCS) Support
Low Voltage Technology
Enhanced Suspend Capabilities
They share a compatible Status Register, basic
software commands, and pinout. These similarities
enable a clean migration from the 28F016SA or
28F016SV. When upgrading, it is important to note
the following differences:
Because of new feature and density options,
the devices have different manufacturer and
device identifier codes. This allows for software
optimization.
New software commands.
To take advantage of low voltage on the
28F160S3 and 28F320S3, allow VPP
connection to VCC. The 28F160S3 and
28F320S3 do not support a 12V VPP option.
1.2 Product Overview
The Word-Wide FlashFile memory family provides
density upgrades with pinout compatibility for the
16- and 32-Mbit densities. They are high-
performance memories arranged as 1 Mword and
2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of
8 bits. This data is grouped in thirty-two and sixty-
four 64-Kbyte blocks that can be erased, locked
and unlocked in-system. Figure 1 shows the block
diagram, and Figure 5 illustrates the memory
organization.
ADVANCE INFORMATION
This family of products are optimized for fast factory
programming and low power designs. Specifically
designed for 3V systems, the 28F160S3 and
28F320S3 support read operations at 2.7V–3.6V
Vcc with block erase and program operations at
2.7V–3.6V and 5V VPP. High programming
performance is achieved through highly-optimized
write buffers. A 5V VPP option is available for even
faster factory programming. For a simple low power
design, VCC and VPP can be tied to 2.7V.
Additionally, the dedicated VPP pin gives complete
data protection when VPP VPPLK.
Internal VPP detection circuitry automatically
configures the device for optimized write
operations.
A Common Flash Interface (CFI) permits OEM-
specified software algorithms to be used for entire
families of devices. This allows device-independent,
JEDEC ID-independent, and forward- and
backward-compatible software support for the
specified flash device families. Flash vendors can
standardize their existing interfaces for long-term
compatibility.
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement).
Additionally, SCS provides the highest
system/device data transfer rates and minimizes
device and system-level implementation costs.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal device operation. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within tWHQV2/EHQV2
independent of other blocks. Each block can be
independently erased 100,000 times. Block erase
suspend mode allows system software to suspend
block erase to read or write data from any other
block.
Data is programmed in byte, word or page
increments. Program suspend mode enables the
system to read data or execute code from any other
flash memory array location.
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28F160S3 arduino
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Commands are written using standard micro-
processor write timings. The CUI contents serve
as input to the WSM that controls the block
erase, programming, and lock-bit configuration.
The internal algorithms are regulated by the
WSM, including pulse repetition, internal
verification, and margining of data. Addresses
and data are internally latched during write
cycles. Writing the appropriate command outputs
array data, identifier codes, or Status Register
data.
Interface software that initiates and polls
progress of block erase, programming, and lock-
bit configuration can be stored in any block. This
code is copied to and executed from system
RAM during flash memory updates. After
successful completion, reads are again possible
via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read or write data from any other
block. Program suspend allows system software
to suspend a program to read data from any
other flash memory array location.
28F160S3, 28F320S3
2.1 Data Protection
Depending on the application, the system
designer may choose to make the VPP power
supply switchable or hardwired to VPPH1/2. The
device supports either design practice, and
encourages optimization of the processor-
memory interface.
When VPP VPPLK, memory contents cannot be
altered. When high voltage is applied to VPP, the
two-step block erase, program, or lock-bit
configuration command sequences provide
protection from unwanted operations. All write
functions are disabled when VCC voltage is below
the write lockout voltage VLKO or when RP# is at
VIL. The device’s block locking capability
provides additional protection from inadvertent
code or data alteration.
Figure 5. Memory Map
ADVANCE INFORMATION
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