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PDF 27LV256 Data sheet ( Hoja de datos )
| Número de pieza | 27LV256 | |
| Descripción | 256K (32K x 8) Low-Voltage CMOS EPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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27LV256
256K (32K x 8) Low-Voltage CMOS EPROM
FEATURES
• Wide voltage range 3.0V to 5.5V
• High speed performance
- 200 ns access time available at 3.0V
• CMOS Technology for low power consumption
- 8 mA Active current at 3.0V
- 20 mA Active current at 5.5V
- 100 µA Standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto ID aids automated programming
• Separate chip enable and output enable controls
• High speed “Express” programming algorithm
• Organized 32K x 8: JEDEC standard pinouts
- 28-pin Dual-in-line package
- 32-pin PLCC package
- 28-pin SOIC package
- 28-pin VSOP package
- Tape and reel
• Data Retention > 200 years
• Available for the following temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial:
-40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 27LV256 is a low volt-
age (3.0 volt) CMOS EPROM designed for battery
powered applications. The device is organized as a
32K x 8 (32K-Byte) non-volatile memory product. The
27LV256 consumes only 8 mA maximum of active cur-
rent during a 3.0 volt read operation therefore improv-
ing battery performance. This device is designed for
very low voltage applications where conventional 5.0
volt only EPROMS can not be used. Accessing individ-
ual bytes from an address transition or from power-up
(chip enable pin going low) is accomplished in less than
200 ns at 3.0V. This device allows systems designers
the ability to use low voltage non-volatile memory with
today’s' low voltage microprocessors and peripherals
in battery powered applications.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount appli-
cations, PLCC, VSOP or SOIC packaging is available.
Tape and reel packaging is also available for PLCC or
SOIC packages.
PACKAGE TYPES
PDIP
VPP • 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
O0 11
O1 12
O2 13
VSS 14
28 VCC
27 A14
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
PLCC
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
O0 13
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 O7
21 O6
SOIC
VPP 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
O0 11
O1 12
O2 13
VSS 14
VSOP
OE 22
A11 23
A9 24
A8 25
A13 26
A14 27
VCC 28
VPP 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
28 VCC
27 A14
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
14 VSS
13 O2
12 O1
11 O0
10 A0
9 A1
8 A2
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS11020F-page 1
1 page  
27LV256
FIGURE 1-2: PROGRAMMING WAVEFORMS
VIH
Address
VIL
VIH
Data
VIL
13.0V(2)
VPP
5.0V
6.5V(2)
VCC
5.0V
VIH
CE
VIL
VIH
OE
VIL
Program
Address Stable
tAS
Data Stable
tDS tDH
tVPS
tVCS
High Z
Verify
tAH
Data Out Valid
tDF
(1)
tPW
tOPW
tOES
tOE
(1)
Notes: (1) tDF and tOE are characteristics of the device but must be accommodated by the programmer
(2) VCC = 6.5V ±0.25V, V PP = VH = 13.0V ±0.25V for express algorithm
TABLE 1-6: MODES
Operation Mode
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
X = Don’t Care
CE OE
VIL VIL
VIL VIH
VIH VIL
VIH VIH
VIH X
VIL VIH
VIL VIL
1.2 Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when:
a) the CE pin is low to power up (enable) the chip
b) the OE pin is low to gate the data to the output
pins
VPP
VCC
VH
VH
VH
VCC
VCC
VCC
A9
X
X
X
X
X
X
VH
O0 - O7
DOUT
DIN
DOUT
High Z
High Z
High Z
Identity Code
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from
CE to output (tCE). Data is transferred to the output
after a delay from the falling edge of OE (tOE).
© 1996 Microchip Technology Inc.
DS11020F-page 5
5 Page 
27LV256
27LV256 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
27LV256 – 25 I /P
Package:
L = Plastic Leaded Chip Carrier
P = Plastic DIP (600 Mil)
SO = Plastic SOIC (300 Mil)
VS = Very Small Outline Package (VSOP) 8X13.4mm
Temperature
Range:
Blank = 0˚C to +70˚C
I = -40˚C to +85˚C
Access
Time:
20 = 200 ns
25 = 250 ns
30 = 300 ns (SOIC only)
Device:
27LV256 256K (32K x 8) Low-Voltage CMOS EPROM
© 1996 Microchip Technology Inc.
DS11020F-page 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 27LV256.PDF ] | |
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