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PDF 27C4100 Data sheet ( Hoja de datos )

Número de pieza 27C4100
Descripción 4M-BIT [512K x 8/256K x 16] CMOS EPROM
Fabricantes Macronix International 
Logotipo Macronix International Logotipo



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MX27C4100/27C4096
4M-BIT [512K x 8/256K x 16] CMOS EPROM
FEATURES
256K x 16 organization(MX27C4096, JEDEC pin
out)
512K x 8 or 256K x 16 organization(MX27C4100,
ROM pin out compatible)
+12.5V programming voltage
Fast access time: 100/120/150 ns
Totally static operation
Completely TTL compatible
Operating current: 60mA
Standby current: 100uA
Package type:
- 40 pin plastic DIP
- 44 pin PLCC
- 40 pin SOP
GENERAL DESCRIPTION
The MX27C4100/4096 is a 5V only, 4M-bit, One Time
Programmable Read Only Memory. It is organized as
256K words by 16 bits per word(MX27C4096), 512K x 8
or 256K x 16(MX27C4100), operates from a single + 5
volt supply, has a static standby mode, and features fast
single address location programming. All programming
signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing EPROM
programmers may be used. The MX27C4100/4096
supports a intelligent fast programming algorithm which
can result in programming time of less than two minutes.
This EPROM is packaged in industry standard 40 pin
dual-in-line packages, 40 lead SOP, and 44 lead PLCC
packages.
PIN CONFIGURATIONS
SOP/PDIP(MX27C4100)
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A8
39 A9
38 A10
37 A11
36 A12
35 A13
34 A14
33 A15
32 A16
31 BYTE/VPP
30 GND
29 Q15/A-1
28 Q7
27 Q14
26 Q6
25 Q13
24 Q5
23 Q12
22 Q4
21 VCC
BLOCK DIAGRAM (MX27C4100)
CE
OE
BYTE/VPP
CONTROL
LOGIC
OUTPUT
BUFFERS
A0~A17
ADDRESS
INPUTS
.
.
.
.
.
.
.
.
VCC
GND
Y-DECODER
X-DECODER
.
.
.
.
.
.
.
.
Y-SELECT
4M BIT
CELL
MAXTRIX
Q0~Q14
Q15/A-1
P/N: PM0197
REV. 3.4, AUG. 22, 2001
1

1 page




27C4100 pdf
MX27C4100/27C4096
BYTE-WIDE MODE
With BYTE/VPP at GND ± 0.2V, outputs Q8-15 are tri-
stated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.
used between VCC and GND for each eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
STANDBY MODE
The MX27C4100/4096 has a CMOS standby mode
which reduces the maximum VCC current to 100 uA. It
is placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX27C4100/4096 also has a TTL-standby mode
which reduces the maximum VCC current to 1.5 mA. It
is placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
P/N: PM0197
REV. 3.4, AUG. 22, 2001
5

5 Page





27C4100 arduino
WEFORMS(MX27C4096)
READ CYCLE(WORD MODE)
ADDRESS
INPUTS
CE
OE
DATA
OUT
MX27C4100/27C4096
tACC
DATA ADDRESS
tCE
VALID DATA
tOE
tDF
tOH
FAST PROGRAMMING ALGORITHM WAVEFORMS
Addresses
VIH
VIL
DATA
VPP
VPP1
VCC
VCC
VCC1
VCC
PROGRAM
tAS
DATA IN STABLE
tDS tDH
tVPS
tVCS
VIH
CE
VIL
OE
VIH
VIL
tPW
Hi-z
PROGRAM VERIFY
tAH
DATA OUT VALID
tDFP
tOES
tOE
Max
P/N: PM0197
REV. 3.4, AUG. 22, 2001
11

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