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PDF 27C256 Data sheet ( Hoja de datos )
| Número de pieza | 27C256 | |
| Descripción | 256K (32K x 8) CMOS EPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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Obsolete Device
27C256
256K (32K x 8) CMOS EPROM
FEATURES
• High speed performance
- 90 ns access time available
• CMOS Technology for low power consumption
- 20 mA Active current
- 100 µA Standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto ID aids automated programming
• Separate chip enable and output enable controls
• High speed “express” programming algorithm
• Organized 32K x 8: JEDEC standard pinouts
- 28-pin Dual-in-line package
- 32-pin PLCC Package
- 28-pin SOIC package
- Tape and reel
• Data Retention > 200 years
• Available for the following temperature ranges:
- Commercial: 0°C to +70°C
- Industrial:
-40°C to +85°C
- Automotive:
-40°C to +125°C
DESCRIPTION
The Microchip Technology Inc. 27C256 is a CMOS
256K bit electrically Programmable Read Only Memory
(EPROM). The device is organized as 32K words by 8
bits (32K bytes). Accessing individual bytes from an
address transition or from power-up (chip enable pin
going low) is accomplished in less than 90 ns. This very
high speed device allows the most sophisticated micro-
processors to run at full speed without the need for
WAIT states. CMOS design and processing enables
this part to be used in systems where reduced power
consumption and reliability are requirements.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount appli-
cations, PLCC, or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages.
PACKAGE TYPES
PLCC
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
O0 13
DIP/SOIC
VPP 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
O0 11
O1 12
O2 13
VSS 14
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 O7
21 O6
28 VCC
27 A14
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
2004 Microchip Technology Inc.
DS11001N-page 1
1 page  
FIGURE 1-2: PROGRAMMING WAVEFORMS
27C256
Address
VIH
VIL
Data
VIH
VIL
13.0V(2)
VPP
5.0V
6.5V(2)
VCC
5.0V
VIH
CE
VIL
VIH
OE
VIL
Program
Address Stable
t AS
Data Stable
tDS tDH
t VPS
t VCS
High Z
Verify
t AH
Data Out Valid
t DF
(1)
t PW
t OES
t OE
(1)
Notes:
(1) tDF and t OE are characteristics of the device but must be accommodated by the programmer
(2) VCC = 6.5 V ±0.25V, V PP = V H = 13.0V ±0.25V for express algorithm
TABLE 1-6: MODES
Operation Mode
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
X = Don’t Care
CE
VIL
VIL
VIH
VIH
VIH
VIL
VIL
OE VPP
VIL VCC
VIH VH
VIL VH
VIH VH
X VCC
VIH VCC
VIL VCC
A9
X
X
X
X
X
X
VH
O0 - O7
DOUT
DIN
DOUT
High Z
High Z
High Z
Identity Code
1.2 Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when:
a) the CE pin is low to power up (enable) the chip
b) the OE pin is low to gate the data to the output
pins
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from
CE to output (tCE). Data is transferred to the output
after a delay from the falling edge of OE (tOE).
2004 Microchip Technology Inc.
DS11001N-page 5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 27C256.PDF ] | |
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