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PDF 27C17A Data sheet ( Hoja de datos )

Número de pieza 27C17A
Descripción 16K (2K x 8) CMOS EEPROM
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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28C17A
16K (2K x 8) CMOS EEPROM
FEATURES
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100 µA Standby
• Fast Byte Write Time—200 µs or 1 ms
• Data Retention >200 years
• High Endurance - Minimum 104 Erase/Write Cycles
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling; Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
- Pulse Filter
- Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 2Kx8 JEDEC Standard Pinout
- 28 Pin Dual-In-Line Package
- 32-Pin PLCC Package
- 28-Pin Thin Small Outline Package (TSOP)
8x20mm
- 28-Pin Very Small Outline Package (VSOP)
8x13.4mm
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 28C17A is a CMOS 16K non-
volatile electrically Erasable PROM. The 28C17A is
accessed like a static RAM for the read or write cycles without
the need of external components. During a “byte write”, the
address and data are latched internally, freeing the micropro-
cessor address and data bus for other operations. Following
the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an
internal control timer. To determine when the write cycle is
complete, the user has a choice of monitoring the Ready/
Busy output or using Data polling. The Ready/Busy pin is an
open drain output, which allows easy configuration in wired-
or systems. Alternatively, Data polling allows the user to read
the location last written to when the write operation is com-
plete. CMOS design and processing enables this part to be
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered
to provide the utmost flexibility in applications.
PACKAGE TYPES
RDY/BSY
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Vcc
27 WE
26 NC
25 A8 A6 5
24 A9 A5 6
23 NC A4 7
22 OE A3 8
21 A10 A2 9
20 CE A1 10
19 I/O7 A0 11
18
I/O6
NC
I/O0
12
13
17 I/O5
16 I/O4
15 I/O3
29 A8
28 A9
27 NC
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
• Pin 1 indicator on PLCC on top of package
OE 1
NC 2
A9 3
A8 4
NC 5
WE 6
Vcc 7
RDY/BSY
NC
A7
A6
A5
A4
A3
8
9
10
11
12
13
14
28 A10
27 CE
26 I/07
25 I/06
24 I/05
23 I/04
22 I/03
21 Vss
20 I/02
19 I/01
18 I/00
17 A0
16 A1
15 A2
OE
NC
A9
A8
NC
WE
VCC
RDY/BSY
NC
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 VSS
13 I/O2
12 I/O1
11 I/O0
10 A0
9 A1
8 A2
BLOCK DIAGRAM
I/O0 I/O7
VSS
VCC
CE
OE
WE
Rdy/
Busy
A0
A10
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Program Voltage
Generation
Data
Poll
Y
L Decoder
a
t
c
h
eX
s Decoder
Input/Output
Buffers
Y Gating
16K bit
Cell Matrix
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS11127G-page 1

1 page




27C17A pdf
28C17A
FIGURE 1-3: DATA POLLING WAVEFORMS
VIH
Address
VIL
VIH
CE
VIL
VIH
WE
VIL
VIH
OE
VIL
VIH
Data
VIL
Address Valid
t WPL
t WPH
t DV
Data In
Valid
t WC
t ACC
t CE
Last Written
Address Valid
t OE
I/O7 Out
True Data Out
FIGURE 1-4: CHIP CLEAR WAVEFORMS
VIH
CE
VIL
VH
OE
VIH
VIH
WE
VIL
tS tH
tW
tW = 10ms
tS = tH = 1µs
VH = 12.0V ±0.5V
TABLE 1-5: SUPPLEMENTARY CONTROL
Mode
Chip Clear
Extra Row Read
Extra Row Write
Note 1: VH = 12.0V ±0.5V
CE
VIL
VIL
*
OE WE A9
VH VIL
X
VIL VIH A9 = VH
VIH * A9 = VH
* Pulsed per programming waveforms.
Vcc I/OI
VCC
VCC Data Out
VCC Data In
© 1996 Microchip Technology Inc.
DS11127G-page 5

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