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PDF 27C020 Data sheet ( Hoja de datos )

Número de pieza 27C020
Descripción 2-Megabit 256K x 8 OTP EPROM
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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No Preview Available ! 27C020 Hoja de datos, Descripción, Manual

AT27C020
Features
Fast Read Access Time - 55 ns
Low Power CMOS Operation
– 100 µA max. Standby
– 25 mA max. Active at 5 MHz
JEDEC Standard Packages
– 32-Lead 600-mil PDIP
– 32-Lead PLCC
– 32-Lead TSOP
5V ± 10% Supply
High-Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
RapidProgramming Algorithm - 100 µs/byte (typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Commercial and Industrial Temperature Ranges
Description
The AT27C020 is a low-power, high performance 2,097,152-bit one-time programma-
ble read only memory (OTP EPROM) organized as 256K by 8 bits. It requires only
one 5V power supply in normal read mode operation. Any byte can be accessed in
less than 55 ns, eliminating the need for speed reducing WAIT states on high perfor-
mance microprocessor systems.
In read mode, the AT27C020 typically consumes 8 mA. Standby mode supply current
is typically less than 10 µA.
Pin Configurations
PLCC Top View
Pin Name
A0 - A17
O0 - O7
CE
OE
PGM
Function
Addresses
Outputs
Chip Enable
Output Enable
Program Strobe
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
O0 13
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 07
2-Megabit
(256K x 8)
OTP EPROM
AT27C020
PDIP Top View
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 PGM
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 07
20 06
19 05
18 04
17 03
TSOP Top View
Type 1
A11
A9
A8
A13
A14
A17
PGM
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 OE
31 A10
30 CE
29 07
28 06
27 05
26 04
25 03
24 GND
23 02
22 01
21 O0
20 A0
19 A1
18 A2
17 A3
Rev. 0570C-B–12/97
1

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27C020 pdf
AC Waveforms for Read Operation(1)
AT27C020
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
Input Test Waveforms and Measurement Levels
For -55 devices only:
3.0V
AC
DRIVING
LEVELS
0.0V
tR, tF < 5 ns (10% to 90%)
1.5V
AC
MEASUREMENT
LEVEL
Output Test Load (1)
For -70,-90,-12,-15 devices only:
Note:
1. CL = 100 pF including jig
capacitance except -55
devices where CL = 30 pF.
tR, tF < 20 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ Max Units
CIN 4 8 pF
COUT
8 12 pF
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Conditions
VIN = 0V
VOUT = 0V
5

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